公开(公告)号：US20200303214A1

公开(公告)日：2020-09-24

申请号：US16896039

申请日：2020-06-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Ling HWANG ,  Bor-Ping JANG ,  Chung-Shi LIU ,  Hsin-Hung LIAO ,  Ying-Jui HUANG

IPC: H01L21/56 ,  H01L23/482 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498

Abstract: A semiconductor package structure includes a molding compound, a micro pin extending through the molding compound, and a die surrounded by the molding compound. The micro pin has a top surface, a bottom surface, and a sidewall extending from the bottom surface to the top surface of the micro pin. The sidewall of the micro pin has a first portion and a second portion. The first portion of the sidewall is adjacent to the bottom surface of the micro pin and free of the molding compound. The second portion of the sidewall is adjacent to the top surface of the micro pin and in contact with the molding compound.

公开(公告)号：US20150024606A1

公开(公告)日：2015-01-22

申请号：US13944257

申请日：2013-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Ling HWANG ,  Bor-Ping JANG ,  Hsin-Hung LIAO ,  Chung-Shi LIU

IPC: H01L21/306 ,  H01L21/308

CPC classification number: H01L21/3083 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/6708 ,  H01L21/682 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: Embodiments of a method for thinning a wafer are provided. The method includes placing a wafer on a support assembly and securing an etching mask to a backside of the wafer. The etching mask covers a peripheral portion of the wafer. The method further includes performing a wet etching process on the backside of the wafer to form a thinned wafer, and the thinned wafer includes peripheral portions having a first thickness and a central portion having a second thickness smaller than the first thickness. Embodiments of system for forming the thinned wafer are also provided.

Abstract translation: 提供了一种用于薄化晶片的方法的实施例。 该方法包括将晶片放置在支撑组件上并将蚀刻掩模固定到晶片的背面。 蚀刻掩模覆盖晶片的周边部分。 该方法还包括在晶片的背面执行湿蚀刻处理以形成薄的晶片，并且薄化的晶片包括具有第一厚度的周边部分和具有小于第一厚度的第二厚度的中心部分。 还提供了用于形成薄化晶片的系统的实施例。

公开(公告)号：US20200303213A1

公开(公告)日：2020-09-24

申请号：US16896038

申请日：2020-06-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Ling HWANG ,  Bor-Ping JANG ,  Chung-Shi LIU ,  Hsin-Hung LIAO ,  Ying-Jui HUANG

IPC: H01L21/56 ,  H01L23/482 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498

Abstract: A method of fabricating a semiconductor package structure is provided. The method includes applying a plurality of first adhesive portions onto a carrier; applying a second adhesive portion onto the carrier; disposing a plurality of micro pins respectively in the first adhesive portions, such that each of the micro pins has a first portion embedded in a corresponding one of the first adhesive portions and a second portion protruding from said corresponding one of the first adhesive portions; bonding a die to the second adhesive portion; forming a molding compound surrounding the micro pins and the die; and removing the carrier from the molding compound after forming the molding compound.

公开(公告)号：US20170352641A1

公开(公告)日：2017-12-07

申请号：US15173816

申请日：2016-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Ling HWANG ,  Hsin-Hung LIAO ,  Yu-Ting CHIU ,  Ching-Hua HSIEH

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/742 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/11334 ,  H01L2224/13017 ,  H01L2224/751 ,  H01L2224/75753 ,  H01L2224/80127 ,  H01L2224/80136 ,  H01L2224/81024 ,  H01L2224/81201 ,  H01L2224/81345 ,  H01L2924/00012

Abstract: A method for mounting components on a substrate is provided. The method includes providing a positioning plate which has a plurality of through holes. The method further includes supplying components each having a longitudinal portion on the positioning plate. The method also includes performing a component alignment process to put the longitudinal portions of the components in the through holes. In addition, the method includes connecting a substrate to the components which have their longitudinal portions in the through holes and removing the positioning plate.

公开(公告)号：US20160240451A1

公开(公告)日：2016-08-18

申请号：US14622484

申请日：2015-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Ling HWANG ,  Bor-Ping JANG ,  Chung-Shi LIU ,  Hsin-Hung LIAO ,  Ying-Jui HUANG

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/482

Abstract: A semiconductor package includes a carrier, at least and adhesive portion, a plurality of micro pins and a die. The carrier has a first surface and second surface opposite to the first surface. The adhesive portion is disposed on the first surface, and the plurality of the micro pins is disposed in the adhesive portions. The die is disposed on the remaining adhesive portion free of the micro pins.

Abstract translation: 半导体封装包括载体，至少和粘合剂部分，多个微销和管芯。 载体具有与第一表面相对的第一表面和第二表面。 粘合剂部分设置在第一表面上，并且多个微销设置在粘合剂部分中。 模具设置在没有微销的剩余粘合剂部分上。

公开(公告)号：US20190074259A1

公开(公告)日：2019-03-07

申请号：US16173992

申请日：2018-10-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ying-Jui HUANG ,  Chung-Shi LIU ,  Hsin-Hung LIAO ,  Chien-Ling HWANG

IPC: H01L23/00 ,  C25D1/22 ,  C25D1/00

Abstract: A conductive micro pin includes a body having a first end surface, a second end surface, a first side surface connecting the first end surface and the second end surface, and a first corner between the first end surface and the first side surface, in which the first side surface is substantially flat, and the first corner is substantially rounded.

公开(公告)号：US20160254239A1

公开(公告)日：2016-09-01

申请号：US14632654

申请日：2015-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ying-Jui HUANG ,  Chung-Shi LIU ,  Hsin-Hung LIAO ,  Chien-Ling HWANG

IPC: H01L23/00 ,  C25D1/00

CPC classification number: H01L24/11 ,  C25D1/00 ,  C25D1/22 ,  H01L24/13 ,  H01L24/64 ,  H01L24/66 ,  H01L2224/11001 ,  H01L2224/1111 ,  H01L2224/11462 ,  H01L2224/11622 ,  H01L2224/13013 ,  H01L2224/13017 ,  H01L2924/2064

Abstract: A method of manufacturing micro pins includes forming a release layer over a substrate. A pattern layer is formed over the release layer, in which the pattern layer has a plurality of openings spaced apart to each other and through the pattern layer. A plurality of micro pins are respectively formed in the openings. The pattern layer and the release layer are removed to obtain the micro pins. An isolated conductive micro pin for connecting one or more components is also provided.

Abstract translation: 制造微销的方法包括在衬底上形成剥离层。 在剥离层上形成图案层，其中图案层具有彼此间隔开并通过图案层的多个开口。 多个微销分别形成在开口中。 去除图案层和剥离层以获得微销。 还提供用于连接一个或多个部件的隔离的导电微销。