公开(公告)号：US20200294944A1

公开(公告)日：2020-09-17

申请号：US16888758

申请日：2020-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hsuan TAI ,  Ting-Ting KUO ,  Yu-Chih HUANG ,  Chih-Wei LIN ,  Hsiu-Jen LIN ,  Chih-Hua CHEN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Hao-Yi TSAI ,  Chung-Shi LIU

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/683

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

公开(公告)号：US20180286823A1

公开(公告)日：2018-10-04

申请号：US15726260

申请日：2017-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hsuan TAI ,  Ting-Ting KUO ,  Yu-Chih HUANG ,  Chih-Wei LIN ,  Hsiu-Jen LIN ,  Chih-Hua CHEN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Hao-Yi TSAI ,  Chung-Shi LIU

IPC: H01L23/00 ,  H01L23/31

Abstract: A method of forming a package structure includes disposing a semiconductor device over a first dielectric layer, wherein a first redistribution line is in the first dielectric layer, forming a molding compound over the first dielectric layer and in contact with a sidewall of the semiconductor device, forming a second dielectric layer over the molding compound and the semiconductor device, forming a first opening in the second dielectric layer, the molding compound, and the first dielectric layer to expose the first redistribution line, and forming a first conductor in the first opening, wherein the first conductor is electrically connected to the first redistribution line.

公开(公告)号：US20170352641A1

公开(公告)日：2017-12-07

申请号：US15173816

申请日：2016-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Ling HWANG ,  Hsin-Hung LIAO ,  Yu-Ting CHIU ,  Ching-Hua HSIEH

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/742 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/11334 ,  H01L2224/13017 ,  H01L2224/751 ,  H01L2224/75753 ,  H01L2224/80127 ,  H01L2224/80136 ,  H01L2224/81024 ,  H01L2224/81201 ,  H01L2224/81345 ,  H01L2924/00012

Abstract: A method for mounting components on a substrate is provided. The method includes providing a positioning plate which has a plurality of through holes. The method further includes supplying components each having a longitudinal portion on the positioning plate. The method also includes performing a component alignment process to put the longitudinal portions of the components in the through holes. In addition, the method includes connecting a substrate to the components which have their longitudinal portions in the through holes and removing the positioning plate.

公开(公告)号：US20180315728A1

公开(公告)日：2018-11-01

申请号：US15499962

申请日：2017-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan PEI ,  Chih-Chiang TSAO ,  Wei-Yu CHEN ,  Hsiu-Jen LIN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Chung-Shi LIU

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56

CPC classification number: H01L24/19 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/293 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/25 ,  H01L24/73 ,  H01L24/96 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68368 ,  H01L2224/13024 ,  H01L2224/19 ,  H01L2224/25171 ,  H01L2224/2518 ,  H01L2224/73209 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/3511

Abstract: Structures and formation methods of a chip package are provided. The method includes forming a protective layer to surround a semiconductor die, and the protective layer has opposing first and second surfaces. The method also includes forming a dielectric layer over the first surface of the protective layer and the semiconductor die. The method further includes forming a conductive feature over the dielectric layer such that the conductive feature is electrically connected to a conductive element of the semiconductor die. In addition, the method includes printing a warpage-control element over the second surface of the protective layer and the semiconductor die such that the semiconductor die is between the warpage-control element and the dielectric layer.

公开(公告)号：US20170317038A1

公开(公告)日：2017-11-02

申请号：US15227060

申请日：2016-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Peng TSAI ,  Sheng-Feng WENG ,  Sheng-Hsiang CHIU ,  Meng-Tse CHEN ,  Chih-Wei LIN ,  Wei-Hung LIN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Chung-Shi LIU

IPC: H01L23/60 ,  H01L25/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H05K9/00 ,  H01L25/065

CPC classification number: H01L23/60 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K9/0073 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a first shielding feature over a base layer. The package structure also includes a package layer encapsulating the integrated circuit die and the first shielding feature. The package structure further includes a second shielding feature extending from the side surface of the base layer towards the first shielding feature to electrically connect to the first shielding feature. The side surface of the second shielding feature faces away from the side surface of the base layer and is substantially coplanar with the side surface of the package layer.

公开(公告)号：US20150206791A1

公开(公告)日：2015-07-23

申请号：US14161247

申请日：2014-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Feng LIN ,  Kuan-Chia CHEN ,  Ching-Hua HSIEH

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76882

Abstract: In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer on a semiconductor substrate. The dielectric layer has at least one first trench in the dielectric layer. The method also includes forming a seed layer on a sidewall and a bottom surface of the first trench. The method further includes forming a first conductive layer on the seed layer. The method includes performing a thermal treatment process to melt and transform the seed layer and the first conductive layer into a second conductive layer. The method also includes forming a third conductive layer on the second conductive layer to fill the first trench.

Abstract translation: 根据一些实施例，提供了一种用于形成半导体器件结构的方法。 该方法包括在半导体衬底上形成电介质层。 电介质层在电介质层中具有至少一个第一沟槽。 该方法还包括在第一沟槽的侧壁和底表面上形成种子层。 该方法还包括在种子层上形成第一导电层。 该方法包括执行热处理工艺以将种子层和第一导电层熔化并变换为第二导电层。 该方法还包括在第二导电层上形成第三导电层以填充第一沟槽。

公开(公告)号：US20200152576A1

公开(公告)日：2020-05-14

申请号：US16741001

申请日：2020-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Da TSAI ,  Cheng-Ping LIN ,  Wei-Hung LIN ,  Chih-Wei LIN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Chung-Shi LIU

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/683 ,  H01L21/56 ,  H01L21/48

Abstract: Package structures and methods for forming the same are provided. The method includes forming a redistribution structure embedded in a passivation layer over a carrier substrate and bonding an integrated circuit die to the redistribution structure through first connectors. The method further includes removing the carrier substrate to expose a bottom portion of the redistribution structure and removing the bottom portion of the redistribution structure to form an opening in the passivation layer. The method further includes forming a second connector over the redistribution structure. In addition, the second connector includes an extending portion extending into the opening in the passivation layer.

公开(公告)号：US20180308800A1

公开(公告)日：2018-10-25

申请号：US16020030

申请日：2018-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Da TSAI ,  Cheng-Ping LIN ,  Wei-Hung LIN ,  Chih-Wei LIN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Chung-Shi LIU

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/29 ,  H01L23/31

Abstract: Package structures and methods for forming the same are provided. A package structure includes a package layer. The package structure also includes an integrated circuit die and a first connector embedded in the package layer. The package structure further includes a redistribution layer over the package layer. The integrated circuit die is electrically connected to the redistribution layer through the first connector. In addition, the package structure includes a passivation layer over the redistribution layer. The package structure also includes a second connector over the passivation layer. A first portion of the redistribution layer and a second portion of the second connector extend into the passivation layer. The second portion of the second connector has a tapered profile along a direction from the integrated circuit die towards the first connector.

公开(公告)号：US20180130749A1

公开(公告)日：2018-05-10

申请号：US15347912

申请日：2016-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Da TSAI ,  Cheng-Ping LIN ,  Wei-Hung LIN ,  Chih-Wei LIN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Chung-Shi LIU

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L23/29

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5386 ,  H01L24/17 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/3511

Abstract: Package structures and methods for forming the same are provided. A method for forming a package structure includes providing a carrier substrate. The method also includes forming a conductive layer over the carrier substrate. The method further includes forming a passivation layer over the conductive layer. The passivation layer includes openings that expose portions of the conductive layer. In addition, the method includes bonding integrated circuit dies to the portions of the conductive layer through bumps. There is a space between the integrated circuit dies and the passivation layer. The method also includes filling the space with a first molding compound. The first molding compound surrounds the bumps and the integrated circuit dies. The method further includes forming a second molding compound capping the first molding compound and the integrated circuit dies. The passivation layer has a sidewall that is covered by the second molding compound.

公开(公告)号：US20170317054A1

公开(公告)日：2017-11-02

申请号：US15237428

申请日：2016-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Chiang TSAO ,  Hsiu-Jen LIN ,  Chun-Cheng LIN ,  Chih-Wei LIN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Chung-Shi LIU

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/50 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2021/6003 ,  H01L2021/60052 ,  H01L2021/6009 ,  H01L2021/60247 ,  H01L2021/60255 ,  H01L2221/68331 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/83

Abstract: A package structure includes a molding material, at least one through-via, at least one conductor, at least one dummy structure and an underfill. The through-via extends through the molding material. The conductor is present on the through-via. The dummy structure is present on the molding material and includes a dielectric material. The underfill is at least partially present between the conductor and the dummy structure.