公开(公告)号：US20240178208A1

公开(公告)日：2024-05-30

申请号：US18192645

申请日：2023-03-30

申请人： TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

发明人： Hongzhao DENG

IPC分类号： H01L25/16 ,  H01L23/00

CPC分类号： H01L25/167 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/16 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/13016 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/81024 ,  H01L2224/81815 ,  H01L2924/12041

摘要： A manufacturing method of a light-emitting substrate and a display device are provided. The manufacturing method includes: providing a substrate provided with a plurality of electrodes, forming a patterned photoresist layer including openings exposing the electrodes on a surface of the substrate, forming connecting parts in the openings, removing the patterned photoresist layer, and bonding a plurality of light-emitting elements on the connecting parts, wherein slope angles of a plurality of connecting part sidewalls of the connecting parts are ranged between 40° and 140°. The method could improve a yield rate of light-emitting elements bonded to electrodes through connecting parts.

公开(公告)号：US11978720B2

公开(公告)日：2024-05-07

申请号：US17347871

申请日：2021-06-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai Jun Zhan ,  Chin-Fu Kao ,  Kuang-Chun Lee ,  Ming-Da Cheng ,  Chen-Shien Chen

IPC分类号： H01L23/00

CPC分类号： H01L24/81 ,  H01L24/16 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/81024 ,  H01L2224/81193 ,  H01L2224/81203

摘要： A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.

公开(公告)号：US11955434B2

公开(公告)日：2024-04-09

申请号：US17861125

申请日：2022-07-08

申请人： Intel Corporation

发明人： Yoshihiro Tomita ,  Eric J. Li ,  Shawna M. Liff ,  Javier A. Falcon ,  Joshua D. Heppner

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/552 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11 ,  H01L25/16

CPC分类号： H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L25/04 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/16 ,  H01L24/16 ,  H01L25/042 ,  H01L25/071 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/112 ,  H01L25/115 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2924/1436 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012

摘要： Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US11727714B2

公开(公告)日：2023-08-15

申请号：US17522610

申请日：2021-11-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chih Huang ,  Chih-Hua Chen ,  Yu-Jen Cheng ,  Chih-Wei Lin ,  Yu-Feng Chen ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： G06V40/13 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC分类号： G06V40/1329 ,  H01L21/561 ,  H01L23/49827 ,  H01L24/19 ,  H01L21/568 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81024 ,  H01L2224/81815 ,  H01L2224/81911 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/85

摘要： A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

公开(公告)号：US11670612B2

公开(公告)日：2023-06-06

申请号：US17176095

申请日：2021-02-15

申请人： Micron Technology, Inc.

发明人： Brandon P. Wirz ,  Benjamin L. McClain ,  Jeremy E. Minnich ,  Zhaohui Ma

IPC分类号： H01L21/48 ,  H01L23/00 ,  H01L21/033 ,  H01L21/60

CPC分类号： H01L24/17 ,  H01L21/0337 ,  H01L24/14 ,  H01L24/81 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2021/60007 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/92125 ,  H01L2224/92125 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor device assembly that includes a semiconductor device positioned over a substrate with a number of electrical interconnections formed between the semiconductor device and the substrate. The surface of the substrate includes a plurality of discrete solder mask standoffs that extend towards the semiconductor device. A thermal compression bonding process is used to melt solder to form the electrical interconnects, which lowers the semiconductor device to contact and be supported by the plurality of discrete solder mask standoffs. The solder mask standoffs permit the application of a higher pressure during the bonding process than using traditional solder masks. The solder mask standoffs may have various polygonal or non-polygonal shapes and may be positioned in pattern to protect sensitive areas of the semiconductor device and/or the substrate. The solder mask standoffs may be an elongated shape that protects areas of the semiconductor device and/or substrate.

公开(公告)号：US20180350767A1

公开(公告)日：2018-12-06

申请号：US16054009

申请日：2018-08-03

申请人： Intel Corporation

发明人： Jonathon R. Carstens ,  Michael S. Brazel ,  Russell S. Aoki ,  Laura S. Mortimer

IPC分类号： H01L23/00 ,  B23K1/00 ,  B23K1/008 ,  B23K1/19 ,  B23K1/20 ,  B23K3/06 ,  B23K3/08 ,  H01L23/34 ,  H01L23/498 ,  B23K101/42 ,  H05K3/12 ,  H05K3/34

CPC分类号： H01L24/81 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/19 ,  B23K1/206 ,  B23K3/06 ,  B23K3/0638 ,  B23K3/082 ,  B23K2101/42 ,  H01L23/345 ,  H01L23/49816 ,  H01L24/75 ,  H01L2224/81007 ,  H01L2224/81024 ,  H01L2224/81035 ,  H01L2224/81234 ,  H01L2224/81815 ,  H01L2924/15321 ,  H05K3/1225 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2203/166

摘要： Reflow Grid Array (RGA) technology may be implemented on an interposer device, where the interposer is placed between a motherboard and a ball grid array (BGA) package. The interposer may provide a controlled heat source to reflow solder between the interposer and the BGA package. A technical problem faced by an interposer using RGA technology is application of solder to the RGA interposer. Technical solutions described herein provide processes and equipment for application of solder and formation of solder balls to connect an RGA interposer to a BGA package.

公开(公告)号：US10076801B2

公开(公告)日：2018-09-18

申请号：US15443347

申请日：2017-02-27

申请人： Samsung Electronics Co., Ltd.

发明人： Min-woo Song ,  Sung-il Cho ,  Se-gi Byun ,  Jin Yu

IPC分类号： B23K1/20 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  C01B31/02 ,  B23K1/19 ,  B82Y40/00 ,  B82Y30/00

CPC分类号： B23K1/203 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/19 ,  B23K2101/42 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/158 ,  H01L21/4853 ,  H01L21/4864 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/81024 ,  H01L2224/81815 ,  H01L2224/81911 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/15311 ,  Y10S977/742 ,  Y10S977/745 ,  Y10S977/75 ,  Y10S977/752 ,  Y10S977/842 ,  Y10S977/89 ,  Y10S977/932

摘要： A method of manufacturing a semiconductor package including coating a flux on a connection pad provided on a first surface of a substrate, the flux including carbon nanotubes (CNTs), placing a solder ball on the connection pad coated with the flux, forming a solder layer attached to the connection pad from the solder ball through a reflow process, and mounting a semiconductor chip on the substrate such that the solder layer faces a connection pad in the semiconductor chip may be provided.

公开(公告)号：US10014272B2

公开(公告)日：2018-07-03

申请号：US14708375

申请日：2015-05-11

申请人： ASM Technology Singapore Pte Ltd

发明人： Dewen Tian ,  Yiu Ming Cheung ,  Ming Li

IPC分类号： H01L23/00

CPC分类号： H01L24/81 ,  H01L24/75 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/751 ,  H01L2224/7525 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/75841 ,  H01L2224/81022 ,  H01L2224/81024 ,  H01L2224/81048 ,  H01L2224/81075 ,  H01L2224/81095 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/8118 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81815 ,  H01L2224/81935 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method of bonding a die comprising solder bumps to a substrate comprising bond pads, the method comprising the steps of heating the die from a first temperature to a second temperature, wherein the first temperature is below the melting point of the solder bumps, and the second temperature is above the melting point of the solder bumps; moving the die relative to the substrate to a first height, whereat the solder bumps contact the bond pads; moving the die further away from the substrate to a second height, while maintaining contact between the solder bumps and bond pads; and thereafter cooling the die from the second temperature to a third temperature to allow the solder bumps to solidify so as to bond the die to the substrate.

公开(公告)号：US09960143B2

公开(公告)日：2018-05-01

申请号：US15253878

申请日：2016-09-01

申请人： TOSHIBA MEMORY CORPORATION

发明人： Soichi Homma ,  Naoyuki Komuta

IPC分类号： H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/81 ,  H01L22/20 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02379 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73207 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/75804 ,  H01L2224/75824 ,  H01L2224/75901 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81048 ,  H01L2224/81121 ,  H01L2224/8118 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/81206 ,  H01L2224/81207 ,  H01L2224/81815 ,  H01L2224/81906 ,  H01L2224/81948 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/3656 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

摘要： A method for manufacturing an electronic component includes positioning a first surface of a first component facing a second surface of a second component in a first state. The first surface has a first pad having a first center. The second surface has a second pad having a second center. At least one of the first or second pads includes a metal member. The method includes melting the metal member and moving the first and second components until the melted metal member contacts both pads, moving at least one of the first or second components in a direction along the first surface, and solidifying the metal member in a second state. A first distance in a direction along the first surface between the first and second centers in the first state is longer than a second distance in the direction between the first and second centers in the second state.

公开(公告)号：US09899286B2

公开(公告)日：2018-02-20

申请号：US15153433

申请日：2016-05-12

申请人： STATS ChipPAC Pte. Ltd.

发明人： Rajendra D. Pendse

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L25/065 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L33/62

CPC分类号： H01L23/3128 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/3178 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1131 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11823 ,  H01L2224/13007 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion.