公开(公告)号：US20210020581A1

公开(公告)日：2021-01-21

申请号：US16514987

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsaing-Pin Kuan ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Yu-Wei Lin ,  Chun-Yen Lan

IPC: H01L23/552 ,  H01L23/28 ,  H01L23/538 ,  H01L21/56 ,  H01L21/768

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, and a redistribution structure. The electromagnetic shielding structure includes a first conductive layer and a dielectric frame laterally covering the first conductive layer. The first conductive layer surrounds the first portion of the insulating encapsulation and extends to cover a first side of the first semiconductor die. The dielectric frame includes a first surface substantially leveled with the first conductive layer. The redistribution structure is disposed on a second side of the first semiconductor die opposing to the first side, and the redistribution structure is electrically coupled to the first semiconductor die and the first conductive layer of the electromagnetic shielding structure.

公开(公告)号：US20210020607A1

公开(公告)日：2021-01-21

申请号：US16513739

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsaing-Pin Kuan ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Ching-Yao Lin ,  Chun-Yen Lan ,  Kai-Ming Chiang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/488 ,  H01L25/00 ,  H01L23/538 ,  H01L23/28

Abstract: A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.

公开(公告)号：US11031376B2

公开(公告)日：2021-06-08

申请号：US16513739

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsaing-Pin Kuan ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Ching-Yao Lin ,  Chun-Yen Lan ,  Kai-Ming Chiang

IPC: H01L23/48 ,  H01L29/40 ,  H01L25/065 ,  H01L23/00 ,  H01L23/28 ,  H01L25/00 ,  H01L23/538 ,  H01L23/488

Abstract: A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.