公开(公告)号：US20230154764A1

公开(公告)日：2023-05-18

申请号：US17655645

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Sung Huang ,  Tsung-Hsien Chiang ,  Ming Hung Tseng ,  Hao-Yi Tsai ,  Yu-Hsiang Hu ,  Chih-Wei Lin ,  Lipu Kris Chuang ,  Wei Lun Tsai ,  Kai-Ming Chiang ,  Ching Yao Lin ,  Chao-Wei Li ,  Ching-Hua Hsieh

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/32

Abstract: A method includes forming a first metal mesh over a carrier, forming a first dielectric layer over the first metal mesh, and forming a second metal mesh over the first dielectric layer. The first metal mesh and the second metal mesh are staggered. The method further includes forming a second dielectric layer over the second metal mesh, attaching a device die over the second dielectric layer, with the device die overlapping the first metal mesh and the second metal mesh, encapsulating the device die in an encapsulant, and forming redistribution lines over and electrically connecting to the device die.

公开(公告)号：US11031376B2

公开(公告)日：2021-06-08

申请号：US16513739

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsaing-Pin Kuan ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Ching-Yao Lin ,  Chun-Yen Lan ,  Kai-Ming Chiang

IPC: H01L23/48 ,  H01L29/40 ,  H01L25/065 ,  H01L23/00 ,  H01L23/28 ,  H01L25/00 ,  H01L23/538 ,  H01L23/488

Abstract: A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.

公开(公告)号：US20210020607A1

公开(公告)日：2021-01-21

申请号：US16513739

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsaing-Pin Kuan ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Ching-Yao Lin ,  Chun-Yen Lan ,  Kai-Ming Chiang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/488 ,  H01L25/00 ,  H01L23/538 ,  H01L23/28

Abstract: A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.