-
公开(公告)号：US10734328B2
公开(公告)日：2020-08-04
申请号：US16714793
申请日：2019-12-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Yuan Teng , Hao-Yi Tsai , Tin-Hao Kuo , Ching-Yao Lin , Teng-Yuan Lo , Chih Wang
Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die disposed on the first redistribution structure, a die attach material disposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure. A first shortest distance from a midpoint of a bottom edge of the semiconductor die to a midpoint of an bottom edge of an extruded region of the die attach material in a width direction of the semiconductor die is greater than a second shortest distance between an endpoint of the bottom edge of the semiconductor die to an endpoint of the bottom edge of the extruded region of the die attach material. The insulating encapsulant encapsulates the semiconductor die and the die attach material. An inclined interface is between the insulating encapsulant and the extruded region of the die attach material.
-
公开(公告)号：US10128193B2
公开(公告)日：2018-11-13
申请号：US15413690
申请日：2017-01-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shing-Chao Chen , Chih-Wei Lin , Ching-Yao Lin , Ming-Da Cheng , Ching-Hua Hsieh
IPC: H01L21/4763 , H01L23/538 , H01L21/48 , H01L21/56 , H01L23/31 , H01L25/10
Abstract: A package structure and methods for forming the same are provided. The package structure includes an integrated circuit die in a package layer. The package structure also includes a first passivation layer covering the package layer and the integrated circuit die, and a second passivation layer over the first passivation layer. The package structure further includes a seed layer and a conductive layer in the second passivation layer. The seed layer covers the top surface of the first passivation layer and extends into the first passivation layer. The conductive layer covers the seed layer and extends into the first passivation layer. In addition, the package structure includes a third passivation layer covering the second passivation layer. The seed layer further extends from the top surface of the first passivation layer to the third passivation layer along a sidewall of the conductive layer.
-
公开(公告)号：US20210020607A1
公开(公告)日：2021-01-21
申请号：US16513739
申请日：2019-07-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsaing-Pin Kuan , Ching-Hua Hsieh , Chih-Wei Lin , Ching-Yao Lin , Chun-Yen Lan , Kai-Ming Chiang
IPC: H01L25/065 , H01L23/00 , H01L23/488 , H01L25/00 , H01L23/538 , H01L23/28
Abstract: A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.
-
公开(公告)号：US10510686B2
公开(公告)日：2019-12-17
申请号：US15964087
申请日：2018-04-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Yuan Teng , Hao-Yi Tsai , Tin-Hao Kuo , Ching-Yao Lin , Teng-Yuan Lo , Chih Wang
Abstract: A semiconductor package and a manufacturing method thereof are provided with the following steps, attaching a rear surface of a semiconductor die on a first redistribution structure by a die attach material, wherein the semiconductor die is pressed so that the die attach material is extruded laterally out and climbs upwardly to cover a sidewall of the semiconductor die, and after attaching, the die attach material comprises an extruded region surrounding the semiconductor die, a first shortest distance from a midpoint of an bottom edge of semiconductor die to a midpoint of an bottom edge of extruded region in a width direction is greater than a second shortest distance between an endpoint of the bottom edge of semiconductor die to an endpoint of the bottom edge of extruded region; and forming an insulating encapsulant on the first redistribution structure to encapsulate the semiconductor die and the die attach material.
-
公开(公告)号：US20190252339A1
公开(公告)日：2019-08-15
申请号：US16396782
申请日：2019-04-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ai-Tee Ang , Shing-Chao Chen , Ching-Hua Hsieh , Chih-Wei Lin , Ching-Yao Lin
IPC: H01L23/00 , H01L21/56 , H01L21/683
CPC classification number: H01L24/19 , H01L21/561 , H01L21/568 , H01L21/6836 , H01L24/11 , H01L24/24 , H01L24/25 , H01L24/96 , H01L2221/68331 , H01L2221/68359 , H01L2221/68368 , H01L2224/1184 , H01L2224/11845 , H01L2224/1191 , H01L2224/18 , H01L2224/24101 , H01L2224/24137 , H01L2224/25171 , H01L2224/73209 , H01L2224/95001
Abstract: A manufacturing method of integrated fan-out package includes following steps. First and second dies are provided on adhesive layer formed on carrier. Heights of first and second dies are different. First and second dies respectively has first and second conductive posts each having substantially a same height. The dies are pressed against adhesive layer to make active surfaces thereof be in direct contact with adhesive layer and conductive posts thereof be submerged into adhesive layer. Adhesive layer is cured. Encapsulant is formed to encapsulate the dies. Carrier is removed from adhesive layer. Heights of first and second conductive posts are reduced and portions of the adhesive layer is removed. First and second conductive posts are laterally wrapped by and exposed from adhesive layer. Top surfaces of first and second conductive posts are leveled. Redistribution structure is formed over adhesive layer and is electrically connected to first and second conductive posts.
-
Patent Agency Ranking
公开(公告)号：US10276537B2
公开(公告)日：2019-04-30
申请号：US15715132
申请日：2017-09-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ai-Tee Ang , Shing-Chao Chen , Ching-Hua Hsieh , Chih-Wei Lin , Ching-Yao Lin
IPC: H01L27/00 , H01L23/00 , H01L21/683 , H01L21/56 , H01L21/00
Abstract: An integrated fan-out package includes a first and second dies, an encapsulant, and a redistribution structure. The first and second dies respectively has an active surface, a rear surface opposite to the active surface, and conductive posts on the active surface. The first and second dies are different types of dies. The active and rear surfaces of the first die are respectively leveled with the active and rear surfaces of the second die. Top surfaces of the conductive posts of the first and second dies are leveled. The conductive posts of the first and second dies are wrapped by same material. The encapsulant encapsulates sidewalls of the first and second dies. A first surface of the encapsulant is leveled with the active surfaces. The second surface of the encapsulant is leveled with the rear surfaces. The redistribution structure is disposed over the first die, the second die, and the encapsulant.
-
公开(公告)号：US11031376B2
公开(公告)日：2021-06-08
申请号：US16513739
申请日：2019-07-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsaing-Pin Kuan , Ching-Hua Hsieh , Chih-Wei Lin , Ching-Yao Lin , Chun-Yen Lan , Kai-Ming Chiang
IPC: H01L23/48 , H01L29/40 , H01L25/065 , H01L23/00 , H01L23/28 , H01L25/00 , H01L23/538 , H01L23/488
Abstract: A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.
-
公开(公告)号：US10985115B2
公开(公告)日：2021-04-20
申请号：US16905928
申请日：2020-06-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Yuan Teng , Hao-Yi Tsai , Tin-Hao Kuo , Ching-Yao Lin , Teng-Yuan Lo , Chih Wang
Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die electrically coupled to the first redistribution structure, a die attach material interposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure and covering the semiconductor die and the die attach material. A bottom of the semiconductor die is embedded in the die attach material, and a thickness of a portion of the die attach material disposed over a spacing of conductive traces of the first redistribution structure is greater than a thickness of another portion of the die attach material disposed over the conductive traces of the first redistribution structure and underlying the bottom of the semiconductor die.
-
公开(公告)号：US20200091091A1
公开(公告)日：2020-03-19
申请号：US16691518
申请日：2019-11-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Yuan Teng , Hao-Yi Tsai , Tin-Hao Kuo , Ching-Yao Lin , Teng-Yuan Lo , Chih Wang
Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A dielectric layer is formed on a conductive pattern and in a space between the conductive pattern, where a concave area of the dielectric layer is formed corresponding to the space between the conductive pattern. A semiconductor die is disposed on the concave area of the dielectric layer with a die attach material interposed therebetween. A pressure is applied to the die attach material so that the concave area of the dielectric layer is filled with the die attach material, and a portion of the die attach material is extruded from the concave area to expand wider than an area of the semiconductor die. An insulating encapsulant is formed on the dielectric layer to cover the semiconductor die. Other methods for forming a semiconductor package are also provided.
-
公开(公告)号：US20190333869A1
公开(公告)日：2019-10-31
申请号：US15964087
申请日：2018-04-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Yuan Teng , Hao-Yi Tsai , Tin-Hao Kuo , Ching-Yao Lin , Teng-Yuan Lo , Chih Wang
Abstract: A semiconductor package and a manufacturing method thereof are provided with the following steps, attaching a rear surface of a semiconductor die on a first redistribution structure by a die attach material, wherein the semiconductor die is pressed so that the die attach material is extruded laterally out and climbs upwardly to cover a sidewall of the semiconductor die, and after attaching, the die attach material comprises an extruded region surrounding the semiconductor die, a first shortest distance from a midpoint of an bottom edge of semiconductor die to a midpoint of an bottom edge of extruded region in a width direction is greater than a second shortest distance between an endpoint of the bottom edge of semiconductor die to an endpoint of the bottom edge of extruded region; and forming an insulating encapsulant on the first redistribution structure to encapsulate the semiconductor die and the die attach material.
-
-
-
-
-
-
-
-
-
Search Results
14
records
(took 0.018 seconds)
