公开(公告)号：US20210249267A1

公开(公告)日：2021-08-12

申请号：US17240692

申请日：2021-04-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Min HSIAO ,  Chien-Wen LAI ,  Shih-Chun HUANG ,  Yung-Sung YEN ,  Chih-Ming LAI ,  Ru-Gun LIU

IPC: H01L21/033

Abstract: A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

公开(公告)号：US20160172297A1

公开(公告)日：2016-06-16

申请号：US15050087

申请日：2016-02-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Liang CHEN ,  Chih-Ming LAI ,  Yung-Sung YEN ,  Kam-Tou SIO ,  Tsong-Hua OU ,  Chun-Kuang CHEN ,  Ru-Gun LIU ,  Shu-Hui SUNG ,  Charles Chew-Yuen YOUNG

IPC: H01L23/528 ,  H01L27/118 ,  H01L27/02 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate. The gate structures follow the following equation: 0.2   P gate   min + 0.35   L gate   min + 0.3   H gate   min - 20 0.2   L gate   min + 0.8   H gate   min - 5 × 0.3   L gate   min + 0.3   H gate   min + 5 38 ≤ 0.32 Pgate min is the minimum value among gate pitches of the gate structures, and Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.

Abstract translation: 提供半导体结构。 半导体结构包括沿着形成在衬底上的第一方向延伸的多个栅极结构。 门结构遵循以下公式：0.2P门min + 0.35min min min min 最小 - 5×0.3英尺L门槛最小+ 0.3H门min + 5 38≤0.32 Pgate min是栅极结构的栅间距中的最小值，Lgate min是 栅极结构的栅极长度。 Hgate min是门结构栅极高度的最小值。

公开(公告)号：US20240096867A1

公开(公告)日：2024-03-21

申请号：US18526395

申请日：2023-12-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen YOUNG ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Jiann-Tyng TZENG ,  Shun-Li CHEN ,  Kam-Tou SIO ,  Shih-Wei PENG ,  Chun-Kuang CHEN ,  Ru-Gun LIU

IPC: H01L27/02 ,  G06F30/394 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485

CPC classification number: H01L27/0207 ,  G06F30/394 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528

Abstract: A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.

公开(公告)号：US20210013048A1

公开(公告)日：2021-01-14

申请号：US17034043

申请日：2020-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun LIU ,  Chih-Ming LAI ,  Wei-Liang LIN ,  Yung-Sung YEN ,  Ken-Hsien HSIEH ,  Chin-Hsiang LIN

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/768

Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.

公开(公告)号：US20190164772A1

公开(公告)日：2019-05-30

申请号：US15967100

申请日：2018-04-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Yuan TSENG ,  Yu-Tien SHEN ,  Wei-Liang LIN ,  Chih-Ming LAI ,  Kuo-Cheng CHING ,  Shi Ning JU ,  Li-Te LIN ,  Ru-Gun LIU

IPC: H01L21/311 ,  H01L21/32

Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.

公开(公告)号：US20190123036A1

公开(公告)日：2019-04-25

申请号：US16216843

申请日：2018-12-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen YOUNG ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Jiann-Tyng TZENG ,  Shun-Li CHEN ,  Kam-Tou SIO ,  Shih-Wei PENG ,  Chun-Kuang CHEN ,  Ru-Gun LIU

IPC: H01L27/02 ,  H01L21/768 ,  H01L21/8234 ,  G06F17/50 ,  H01L23/485

Abstract: Gate structures extending continuously above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure are arranged. At least one local interconnect over the non-active region and between two of the gate structures is selectively arranged, to couple at least one of contacts that is arranged above the first active region to at least one of the contacts that is arranged above the second active region.

公开(公告)号：US20210066091A1

公开(公告)日：2021-03-04

申请号：US16894545

申请日：2020-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Min HSIAO ,  Chien-Wen LAI ,  Ru-Gun LIU ,  Chih-Ming LAI ,  Wei-Shuo SU ,  Yu-Chen CHANG

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/768

Abstract: A four signal line unit cell is formed on a substrate using a combination of an extreme ultraviolet photolithography process and one or more self aligned deposition processes. The photolithography process and the self aligned deposition processes result in spacers on a hard mask above the substrate. The spacers define a pattern of signal lines to be formed on the substrate for a unit cell. The photolithography process and self aligned deposition processes result in signal lines having a critical dimension much smaller than features that can be defined by the extreme ultraviolet photolithography process.

公开(公告)号：US20210064806A1

公开(公告)日：2021-03-04

申请号：US16850849

申请日：2020-04-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Wei PENG ,  Chih-Ming LAI ,  Jiann-Tyng TZENG

IPC: G06F30/392 ,  H01L23/538

Abstract: A method of generating an integrated circuit (IC) layout diagram includes arranging first conductive feature layout patterns in a cell region. The first conductive feature layout patterns extend in a first direction, and the cell region has opposite first and second cell boundaries extending in a second direction. Second conductive feature layout patterns are arranged in the cell region and extending in the first direction. The first and second conductive feature layout patterns are alternately arranged. First cut feature layout patterns are arranged on the first cell boundary of the cell region and on ends of the first conductive feature layout patterns. One of the first cut feature layout patterns is offset from another one of the first cut feature layout patterns in the first direction. The IC layout diagram including the first and second conductive feature layout patterns and the first cut feature layout patterns is generated.

公开(公告)号：US20200066523A1

公开(公告)日：2020-02-27

申请号：US16669065

申请日：2019-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming LAI ,  Shih-Ming CHANG ,  Wei-Liang LIN ,  Chin-Yuan TSENG ,  Ru-Gun LIU

IPC: H01L21/033 ,  H01L21/311

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming first spacers over inner walls of the trench. The method includes removing a portion of the first spacers. The method includes forming a filling layer into the trench to cover the first spacers. The filling layer and the first spacers together form a strip structure. The method includes removing the first layer. The method includes forming second spacers over two opposite first sidewalls of the strip structure.

公开(公告)号：US20200006078A1

公开(公告)日：2020-01-02

申请号：US16240402

申请日：2019-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun LIU ,  Chih-Ming LAI ,  Wei-Liang LIN ,  Yung-Sung YEN ,  Ken-Hsien HSIEH ,  Chin-Hsiang LIN

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/768

Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.