公开(公告)号：US20220020738A1

公开(公告)日：2022-01-20

申请号：US16933570

申请日：2020-07-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-An LAI ,  Shih-Wei PENG ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L27/02 ,  H03K19/17736 ,  H01L23/522 ,  H01L21/8238

Abstract: An integrated circuit includes a semiconductor substrate, transistors on the semiconductor, horizontal routing tracks extending in a first direction in a first metal layer, and one or more backside routing tracks extending in the first direction in a backside metal layer. Each transistor has a gate terminal, a source terminal, and a drain terminal. A first transistor has a first terminal, a second terminal, and a third terminal. A first horizontal routing track of the horizontal routing tracks is conductively connected to the first terminal of the first transistor through a via connector. A first backside routing track is conductively connected to the second terminal of the first transistor through a backside via connector. The backside metal layer and the first metal layer are formed at opposite sides of the semiconductor substrate.

公开(公告)号：US20190096909A1

公开(公告)日：2019-03-28

申请号：US16022821

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Cheng-Chi CHUANG ,  Chih-Ming LAI ,  Chia-Tien WU ,  Charles Chew-Yuen YOUNG ,  Hui-Ting YANG ,  Jiann-Tyng TZENG ,  Ru-Gun LIU ,  Wei-Cheng LIN ,  Lei-Chun CHOU ,  Wei-An LAI

IPC: H01L27/118 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

公开(公告)号：US20240178139A1

公开(公告)日：2024-05-30

申请号：US18437130

申请日：2024-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-An LAI ,  Shih-Wei PENG ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L23/528 ,  G06F30/31 ,  G06F30/394 ,  G06F30/398 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L23/528 ,  G06F30/394 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696 ,  G06F30/31 ,  G06F30/398

Abstract: Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.