公开(公告)号：US20210249267A1

公开(公告)日：2021-08-12

申请号：US17240692

申请日：2021-04-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Min HSIAO ,  Chien-Wen LAI ,  Shih-Chun HUANG ,  Yung-Sung YEN ,  Chih-Ming LAI ,  Ru-Gun LIU

IPC: H01L21/033

Abstract: A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

公开(公告)号：US20210019464A1

公开(公告)日：2021-01-21

申请号：US17063429

申请日：2020-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ping CHIANG ,  Ming-Hui CHIH ,  Chih-Wei HSU ,  Ping-Chieh WU ,  Ya-Ting CHANG ,  Tsung-Yu WANG ,  Wen-Li CHENG ,  Hui En YIN ,  Wen-Chun HUANG ,  Ru-Gun LIU ,  Tsai-Sheng GAU

IPC: G06F30/39 ,  G03F1/70 ,  G03F7/20

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

公开(公告)号：US20200057375A1

公开(公告)日：2020-02-20

申请号：US16534965

申请日：2019-08-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shinn-Sheng YU ,  Ru-Gun LIU ,  Hsu-Ting HUANG ,  Chin-Hsiang LIN

IPC: G03F7/20 ,  G03F1/22 ,  G03F1/26 ,  G03F1/00

Abstract: An extreme ultraviolet lithography (EUVL) method includes providing at least two phase-shifting mask areas having a same pattern. A resist layer is formed over a substrate. An optimum exposure dose of the resist layer is determined, and a latent image is formed on a same area of the resist layer by a multiple exposure process. The multiple exposure process includes a plurality of exposure processes and each of the plurality of exposure processes uses a different phase-shifting mask area from the at least two phase-shifting mask areas having a same pattern.

公开(公告)号：US20190341254A1

公开(公告)日：2019-11-07

申请号：US16512336

申请日：2019-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Chun HUANG ,  Chin-Hsiang LIN ,  Chien-Wen LAI ,  Ru-Gun LIU ,  Wei-Liang LIN ,  Ya Hui CHANG ,  Yung-Sung YEN ,  Yu-Tien SHEN ,  Ya-Wen YEH

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/3105

Abstract: A method of fabricating a semiconductor device includes forming a hard mask layer over a substrate. A multi-layer resist is formed over the hard mask layer. The multi-layer resist is etched to form a plurality of openings in the multi-layer resist to expose a portion of the hard mask layer. Ion are directionally provided at an angle to the multi-layer resist to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In one embodiment, the multi-layer resist is directionally etched by directing etch ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In another embodiment, the multi-layer resist is directionally implanted by directing implant ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer.

公开(公告)号：US20190146328A1

公开(公告)日：2019-05-16

申请号：US16144882

申请日：2018-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Ting HUANG ,  Shih-Hsiang LO ,  Ru-Gun LIU

IPC: G03F1/36 ,  G06F17/50 ,  G03F7/20 ,  G03F1/72

Abstract: A method for mask data synthesis and mask making includes calibrating an optical proximity correction (OPC) model by adjusting a plurality of parameters including a first parameter and a second parameter, wherein the first parameter indicates a long-range effect caused by an electron-beam lithography tool for making a mask used to manufacture a structure, and the second parameter indicates a geometric feature of a structure or a manufacturing process to make the structure, generating a device layout, calculating a first grid pattern density map of the device layout, generating a long-range correction map, at least based on the calibrated OPC model and the first grid pattern density map of the device layout, and performing an OPC to generate a corrected mask layout, at least based on the generated long-range correction map and the calibrated OPC model.

公开(公告)号：US20190115261A1

公开(公告)日：2019-04-18

申请号：US16206803

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jui-Yao LAI ,  Ying-Yan CHEN ,  Yen-Ming CHEN ,  Sai-Hooi YEONG ,  Yung-Sung YEN ,  Ru-Gun LIU

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L23/535 ,  H01L29/06

Abstract: A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.

公开(公告)号：US20180149982A1

公开(公告)日：2018-05-31

申请号：US15398839

申请日：2017-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming CHANG ,  Ru-Gun LIU ,  Shuo-Yen CHOU ,  Chien-Wen LAI ,  Zengqin ZHAO

IPC: G03F7/20 ,  G03F7/038 ,  G03F7/039 ,  G03F7/34

CPC classification number: G03F7/70641 ,  G03F7/038 ,  G03F7/039 ,  G03F7/2004 ,  G03F7/34

Abstract: A pattern modification method and a patterning process are provided. The method includes extracting a first pattern and a second pattern to be respectively transferred to a first target portion and a second target portion of a resist layer. The method also includes obtaining regional information of the first target portion and the second target portion. The method includes determining a first desired focus position for transferring the first pattern based on the regional information. In addition, the method includes determining a second desired focus position for transferring the second pattern based on the regional information. The method includes modifying one or both of the first pattern and the second pattern. As a result, focus positions of the first pattern and the second pattern are shifted to be substantially and respectively positioned at the first desired focus position and the second desired focus position during an exposure operation.

公开(公告)号：US20170160633A1

公开(公告)日：2017-06-08

申请号：US15436729

申请日：2017-02-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Yu LIN ,  Yi-Jie CHEN ,  Feng-Yuan CHIU ,  Ying-Chou CHENG ,  Kuei-Liang LU ,  Ya-Hui CHANG ,  Ru-Gun LIU ,  Tsai-Sheng GAU

IPC: G03F1/42 ,  G03F7/038 ,  G06F17/50 ,  G03F1/36

CPC classification number: G03F1/42 ,  G03F1/36 ,  G03F7/038 ,  G06F17/5072

Abstract: A photomask and method for fabricating an integrated circuit is provided. A design layout is provided, wherein the design layout has a plurality of main features. A plurality of assistant features are added in an assistant region of the design layout to form a first layout, wherein the assistant region has no main feature and a width of the assistant region is larger than five times of a width of the main feature. A plurality of optical proximity correction (OPC) features are added on the first layout to form a second layout. And a photomask is formed according to the second layout.

公开(公告)号：US20160172297A1

公开(公告)日：2016-06-16

申请号：US15050087

申请日：2016-02-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Liang CHEN ,  Chih-Ming LAI ,  Yung-Sung YEN ,  Kam-Tou SIO ,  Tsong-Hua OU ,  Chun-Kuang CHEN ,  Ru-Gun LIU ,  Shu-Hui SUNG ,  Charles Chew-Yuen YOUNG

IPC: H01L23/528 ,  H01L27/118 ,  H01L27/02 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate. The gate structures follow the following equation: 0.2   P gate   min + 0.35   L gate   min + 0.3   H gate   min - 20 0.2   L gate   min + 0.8   H gate   min - 5 × 0.3   L gate   min + 0.3   H gate   min + 5 38 ≤ 0.32 Pgate min is the minimum value among gate pitches of the gate structures, and Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.

Abstract translation: 提供半导体结构。 半导体结构包括沿着形成在衬底上的第一方向延伸的多个栅极结构。 门结构遵循以下公式：0.2P门min + 0.35min min min min 最小 - 5×0.3英尺L门槛最小+ 0.3H门min + 5 38≤0.32 Pgate min是栅极结构的栅间距中的最小值，Lgate min是 栅极结构的栅极长度。 Hgate min是门结构栅极高度的最小值。

公开(公告)号：US20240096867A1

公开(公告)日：2024-03-21

申请号：US18526395

申请日：2023-12-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen YOUNG ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Jiann-Tyng TZENG ,  Shun-Li CHEN ,  Kam-Tou SIO ,  Shih-Wei PENG ,  Chun-Kuang CHEN ,  Ru-Gun LIU

IPC: H01L27/02 ,  G06F30/394 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485

CPC classification number: H01L27/0207 ,  G06F30/394 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528

Abstract: A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.