公开(公告)号：US09679980B2

公开(公告)日：2017-06-13

申请号：US14208905

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  I-Ting Li ,  Ming-Hsiang Kao

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11521 ,  G11C16/04

CPC classification number: H01L29/42328 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

Abstract: The present disclosure relates to an embedded flash memory cell having a common source oxide layer with a substantially flat top surface, disposed between a common source region and a common erase gate, and a method of formation. In some embodiments, the embedded flash memory cell has a semiconductor substrate with a common source region separated from a first drain region by a first channel region and separated from a second drain region by a second channel region. A high-quality common source oxide layer is formed by an in-situ steam generation (ISSG) process at a location overlying the common source region. First and second floating gate are disposed over the first and second channel regions on opposing sides of a common erase gate having a substantially flat bottom surface abutting a substantially flat top surface of the common source oxide layer.

公开(公告)号：US20150263123A1

公开(公告)日：2015-09-17

申请号：US14208905

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  I-Ting Li ,  Ming-Hsiang Kao

IPC: H01L29/51 ,  H01L29/788 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L29/42328 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

Abstract: The present disclosure relates to an embedded flash memory cell having a common source oxide layer with a substantially flat top surface, disposed between a common source region and a common erase gate, and a method of formation. In some embodiments, the embedded flash memory cell has a semiconductor substrate with a common source region separated from a first drain region by a first channel region and separated from a second drain region by a second channel region. A high-quality common source oxide layer is formed by an in-situ steam generation (ISSG) process at a location overlying the common source region. First and second floating gate are disposed over the first and second channel regions on opposing sides of a common erase gate having a substantially flat bottom surface abutting a substantially flat top surface of the common source oxide layer.

Abstract translation: 本公开涉及一种具有公共源极氧化物层的嵌入式闪存单元，其具有基本上平坦的顶表面，设置在公共源极区域和公共擦除栅极之间以及形成方法。 在一些实施例中，嵌入式闪存单元具有半导体衬底，其具有通过第一沟道区与第一漏极区分离的公共源极区，并且通过第二沟道区与第二漏极区分离。 通过原位蒸汽发生（ISSG）工艺在覆盖共同源极区域的位置形成高质量的共源氧化物层。 第一和第二浮栅设置在公共擦除栅极的相对侧上的第一和第二沟道区域上，该公共栅极具有与公共源极氧化物层的基本上平坦的顶表面邻接的基本平坦的底表面。