公开(公告)号：US11296209B2

公开(公告)日：2022-04-05

申请号：US16815131

申请日：2020-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu

IPC: H01L29/66 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02 ,  H01L21/311

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated circuit (IC). The method includes forming a gate electrode and a gate dielectric stacked over a substrate. A sidewall spacer layer is deposited over the substrate and the gate electrode, in which the sidewall spacer layer lines sidewalls of the gate electrode. An etching back is performed on the sidewall spacer layer to form a sidewall spacer on the sidewalls of the gate electrode. The etching back is performed at an etch rate less than about 8 angstroms/minute using an etchant comprising hydrogen fluoride. Further, the substrate is doped with the sidewall spacer and the gate electrode in place to form a pair of source/drain regions respectively on opposite sides of the gate electrode.

公开(公告)号：US11264469B2

公开(公告)日：2022-03-01

申请号：US16861478

申请日：2020-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuo-Hwa Tzeng ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L29/40 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/324 ,  H01L21/66 ,  H01L21/311

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

公开(公告)号：US20210098281A1

公开(公告)日：2021-04-01

申请号：US16812533

申请日：2020-03-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Kuan-Liang Liu

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12

Abstract: The present disclosure, in some embodiments, relates to a method of forming a semiconductor structure. The method includes forming a plurality of bulk micro defects within a handle substrate. Sizes of the plurality of bulk micro defects are increased to form a plurality of bulk macro defects (BMDs) within the handle substrate. Some of the plurality of BMDs are removed from within a first denuded region and a second denuded region arranged along opposing surfaces of the handle substrate. An insulating layer is formed onto the handle substrate. A device layer comprising a semiconductor material is formed onto the insulating layer. The first denuded region and the second denuded region vertically surround a central region of the handle substrate that has a higher concentration of the plurality of BMDs than both the first denuded region and the second denuded region.

公开(公告)号：US20200006385A1

公开(公告)日：2020-01-02

申请号：US16024962

申请日：2018-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Min-Ying Tsai ,  Alex Usenko

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/762 ,  H01L21/84 ,  H01L29/04 ,  H01L29/16

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes, as well as the resulting SOI substrate. In some embodiments, an amorphous silicon layer is deposited on a high-resistivity substrate. A rapid thermal anneal (RTA) is performed to crystallize the amorphous silicon layer into a trap-rich layer of polysilicon in which a majority of grains are equiaxed. An insulating layer is formed over the trap-rich layer. A device layer is formed over the insulating layer and comprises a semiconductor material. Equiaxed grains are smaller than other grains (e.g., columnar grains). Since a majority of grains in the trap-rich layer are equiaxed, the trap-rich layer has a high grain boundary area and a high density of carrier traps. The high density of carrier traps may, for example, reduce the effects of parasitic surface conduction (PSC).

公开(公告)号：US10163647B2

公开(公告)日：2018-12-25

申请号：US15416733

申请日：2017-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Ying Tsai ,  Cheng-Ta Wu ,  Yeur-Luen Tu

IPC: H01L21/308 ,  H01L21/3065 ,  H01L49/02 ,  H01L27/146

Abstract: A method for forming a deep trench structure is provided. The method includes forming a first recess in a top portion of a substrate and forming a first protective layer on sidewalls of the first recess. The method includes etching a middle portion of the substrate by using the first protective layer as a mask to form a second recess and forming a second protective layer on sidewalls of the second recess. The method also includes etching a bottom portion of the substrate by using the second protective layer as a mask to form a third recess; and removing the first protective layer and the second protective layer to form a deep trench structure. The deep trench structure is constructed by the first recess, the second recess and the third recess, and the deep trench structure has a stair shape.

公开(公告)号：US10026838B2

公开(公告)日：2018-07-17

申请号：US15054086

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Yung-Yu Wang ,  Yung-Hsiang Chan ,  Chia-Ying Tsai ,  Ting-Chun Wang

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and strained source and drain regions is described. The at least one gate structure is disposed over the substrate and on the isolation structures. The spacers are disposed on sidewalls of the at least one gate structure. First blocking material layers are disposed on the spacers. The strained source and drain regions are disposed at two opposite sides of the at least one gate structure. Second blocking material layers are disposed on the strained source and drain regions. The first and second blocking material layers comprise oxygen-rich oxide materials.

公开(公告)号：US09728646B2

公开(公告)日：2017-08-08

申请号：US14925846

申请日：2015-10-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Shiu-Ko Jangjian ,  Cheng-Wei Chen ,  Ting-Chun Wang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7854 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848

Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile by the thermal hydrogen treatment.

公开(公告)号：US12119267B2

公开(公告)日：2024-10-15

申请号：US18151412

申请日：2023-01-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Cheng Chou ,  Shiu-Ko Jangjian ,  Cheng-Ta Wu

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/02164 ,  H01L21/02304 ,  H01L21/02312 ,  H01L21/3247 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886

Abstract: A method includes forming patterned masks over a semiconductor substrate; etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins; performing an annealing process using a hydrogen containing gas to smooth surfaces of the semiconductor fins; after performing the annealing process, selectively forming a first liner on the smoothed surfaces of the semiconductor fins, while leaving surfaces of the patterned masks exposed by the first liner; filling the trench with a dielectric material; and etching back the first liner and the dielectric material to form an isolation structure between the semiconductor fins.

公开(公告)号：US11594597B2

公开(公告)日：2023-02-28

申请号：US16663659

申请日：2019-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Po-Wei Liu ,  Yeur-Luen Tu ,  Yu-Chun Chang

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/763

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.

公开(公告)号：US11495489B2

公开(公告)日：2022-11-08

申请号：US16732696

申请日：2020-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuan-Liang Liu ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L21/00 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/306

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.