公开(公告)号：US20230154843A1

公开(公告)日：2023-05-18

申请号：US17674459

申请日：2022-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Zhong Chen ,  JeiMing Chen ,  Tze-Liang Lee

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L28/92 ,  H01L28/91 ,  H01L23/5226 ,  H01L21/76877 ,  H01L21/76829

Abstract: A semiconductor device includes: a substrate; an interconnect structure over the substrate; an etch stop layer over the interconnect structure; and metal-insulator-metal (MIM) capacitors over the etch stop layer. The MIM capacitors includes: a bottom electrode extending along the etch stop layer, where the bottom electrode has a layered structure that includes a first conductive layer, a second conductive layer, and a third conductive layer between the first conductive layer and the second conductive layer, where the first conductive layer and the second conductive layer include a first material, and the third conductive layer includes a second material different from the first material; a first dielectric layer over the bottom electrode; a middle electrode over the first dielectric layer, where the middle electrode has the layered structure; a second dielectric layer over the middle electrode; and a top electrode over the second dielectric layer.

公开(公告)号：US20220102143A1

公开(公告)日：2022-03-31

申请号：US17332553

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Kai Chen ,  JeiMing Chen ,  Tze-Liang Lee

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

Abstract: A method includes forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa, patterning the metal-containing hard mask layer to form an opening in the metal-containing hard mask layer, and etching the dielectric layer using the metal-containing hard mask layer as an etching mask. The opening extends into the dielectric layer. The opening is filled with a conductive material to form a conductive feature. The metal-containing hard mask layer is then removed.

公开(公告)号：US20250079172A1

公开(公告)日：2025-03-06

申请号：US18953928

申请日：2024-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Kai Chen ,  JeiMing Chen ,  Tze-Liang Lee

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

Abstract: A method includes forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa, patterning the metal-containing hard mask layer to form an opening in the metal-containing hard mask layer, and etching the dielectric layer using the metal-containing hard mask layer as an etching mask. The opening extends into the dielectric layer. The opening is filled with a conductive material to form a conductive feature. The metal-containing hard mask layer is then removed.

公开(公告)号：US12183577B2

公开(公告)日：2024-12-31

申请号：US17332553

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Kai Chen ,  JeiMing Chen ,  Tze-Liang Lee

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

Abstract: A method includes forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa, patterning the metal-containing hard mask layer to form an opening in the metal-containing hard mask layer, and etching the dielectric layer using the metal-containing hard mask layer as an etching mask. The opening extends into the dielectric layer. The opening is filled with a conductive material to form a conductive feature. The metal-containing hard mask layer is then removed.

公开(公告)号：US20230154753A1

公开(公告)日：2023-05-18

申请号：US17686184

申请日：2022-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hau Shiu ,  Ching-Yu Chang ,  Wei-Ren Wang ,  JeiMing Chen

IPC: H01L21/033 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/31116 ,  H01L21/31144

Abstract: Methods of patterning semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a first dielectric layer over a semiconductor substrate; forming a first hard mask layer over the first dielectric layer; etching the first hard mask layer to form a first opening exposing a top surface of the first dielectric layer; performing a plasma treatment process on the top surface of the first dielectric layer and a top surface of the first hard mask layer; after performing the plasma treatment process, selectively depositing a spacer on a side surface of the first hard mask layer, the top surface of the first dielectric layer and the top surface of the first hard mask layer being free from the spacer after selectively depositing the spacer; and etching the first dielectric layer using the spacer as a mask.

公开(公告)号：US20240387616A1

公开(公告)日：2024-11-21

申请号：US18781476

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Zhong Chen ,  JeiMing Chen ,  Tze-Liang Lee

IPC: H01G4/30

Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming an etch stop layer over the interconnect structure; and forming a first multi-layered structure over the etch stop layer, which includes: forming a first conductive layer over the etch stop layer; treating an upper layer of the first conductive layer with a plasma process; and forming a second conductive layer over the treated first conductive layer. The method further includes: patterning the first multi-layered structure to form a first electrode; forming a first dielectric layer over the first electrode; forming a second multi-layered structure over the first dielectric layer, the second multi-layered structure having the same layered structure as the first multi-layered structure; and patterning the second multi-layered structure to form a second electrode.

公开(公告)号：US20230163163A1

公开(公告)日：2023-05-25

申请号：US17717731

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Zhong Chen ,  JeiMing Chen ,  Tze-Liang Lee

IPC: H01L49/02

CPC classification number: H01L28/87

Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming an etch stop layer over the interconnect structure; and forming a first multi-layered structure over the etch stop layer, which includes: forming a first conductive layer over the etch stop layer; treating an upper layer of the first conductive layer with a plasma process; and forming a second conductive layer over the treated first conductive layer. The method further includes: patterning the first multi-layered structure to form a first electrode; forming a first dielectric layer over the first electrode; forming a second multi-layered structure over the first dielectric layer, the second multi-layered structure having the same layered structure as the first multi-layered structure; and patterning the second multi-layered structure to form a second electrode.