公开(公告)号：US12057450B2

公开(公告)日：2024-08-06

申请号：US17818627

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chi Tai ,  Yi-Fang Pai ,  Tsz-Mei Kwok ,  Tsung-Hsi Yang ,  Jeng-Wei Yu ,  Cheng-Hsiung Yen ,  Jui-Hsuan Chen ,  Chii-Horng Li ,  Yee-Chia Yeo ,  Heng-Wen Ting ,  Ming-Hua Yu

IPC: H01L29/94 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/76 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

公开(公告)号：US11652105B2

公开(公告)日：2023-05-16

申请号：US17143681

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chi Tai ,  Yi-Fang Pai ,  Tsz-Mei Kwok ,  Tsung-Hsi Yang ,  Jeng-Wei Yu ,  Cheng-Hsiung Yen ,  Jui-Hsuan Chen ,  Chii-Horng Li ,  Yee-Chia Yeo ,  Heng-Wen Ting ,  Ming-Hua Yu

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

公开(公告)号：US20240355826A1

公开(公告)日：2024-10-24

申请号：US18760800

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chi Tai ,  Yi-Fang Pai ,  Tsz-Mei Kwok ,  Tsung-Hsi Yang ,  Jeng-Wei Yu ,  Cheng-Hsiung Yen ,  Jui-Hsuan Chen ,  Chii-Horng Li ,  Yee-Chia Yeo ,  Heng-Wen Ting ,  Ming-Hua Yu

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

公开(公告)号：US20220384437A1

公开(公告)日：2022-12-01

申请号：US17818627

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chi Tai ,  Yi-Fang Pai ,  Tsz-Mei Kwok ,  Tsung-Hsi Yang ,  Jeng-Wei Yu ,  Cheng-Hsiung Yen ,  Jui-Hsuan Chen ,  Chii-Horng Li ,  Yee-Chia Yeo ,  Heng-Wen Ting ,  Ming-Hua Yu

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

公开(公告)号：US20220028856A1

公开(公告)日：2022-01-27

申请号：US17143681

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chi Tai ,  Yi-Fang Pai ,  Tsz-Mei Kwok ,  Tsung-Hsi Yang ,  Jeng-Wei Yu ,  Cheng-Hsiung Yen ,  Jui-Hsuan Chen ,  Chii-Horng Li ,  Yee-Chia Yeo ,  Heng-Wen Ting ,  Ming-Hua Yu

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.