公开(公告)号：US12094761B2

公开(公告)日：2024-09-17

申请号：US18342855

申请日：2023-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ru Lee ,  Chii-Horng Li ,  Chien-I Kuo ,  Li-Li Su ,  Chien-Chang Su ,  Heng-Wen Ting ,  Jung-Chi Tai ,  Che-Hui Lee ,  Ying-Wei Li

IPC: H01L21/82 ,  H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/764 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7853

Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

公开(公告)号：US12002854B2

公开(公告)日：2024-06-04

申请号：US17520983

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Heng-Wen Ting ,  Kei-Wei Chen ,  Chii-Horng Li ,  Pei-Ren Jeng ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Chun-An Lin

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.

公开(公告)号：US20220384437A1

公开(公告)日：2022-12-01

申请号：US17818627

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chi Tai ,  Yi-Fang Pai ,  Tsz-Mei Kwok ,  Tsung-Hsi Yang ,  Jeng-Wei Yu ,  Cheng-Hsiung Yen ,  Jui-Hsuan Chen ,  Chii-Horng Li ,  Yee-Chia Yeo ,  Heng-Wen Ting ,  Ming-Hua Yu

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

公开(公告)号：US20220028856A1

公开(公告)日：2022-01-27

申请号：US17143681

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chi Tai ,  Yi-Fang Pai ,  Tsz-Mei Kwok ,  Tsung-Hsi Yang ,  Jeng-Wei Yu ,  Cheng-Hsiung Yen ,  Jui-Hsuan Chen ,  Chii-Horng Li ,  Yee-Chia Yeo ,  Heng-Wen Ting ,  Ming-Hua Yu

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

公开(公告)号：US20250006549A1

公开(公告)日：2025-01-02

申请号：US18885851

申请日：2024-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ru Lee ,  Chii-Horng Li ,  Chien-I Kuo ,  Li-Li Su ,  Chien-Chang Su ,  Heng-Wen Ting ,  Jung-Chi Tai ,  Che-Hui Lee ,  Ying-Wei Li

IPC: H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78

Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

公开(公告)号：US20230343635A1

公开(公告)日：2023-10-26

申请号：US18342855

申请日：2023-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ru Lee ,  Chii-Horng Li ,  Chien-I Kuo ,  Li-Li Su ,  Chien-Chang Su ,  Heng-Wen Ting ,  Jung-Chi Tai ,  Che-Hui Lee ,  Ying-Wei Li

IPC: H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/24 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/764 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/24 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7851 ,  H01L29/7848 ,  H01L29/66795 ,  H01L29/7853

Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

公开(公告)号：US11728208B2

公开(公告)日：2023-08-15

申请号：US17315842

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ru Lee ,  Chii-Horng Li ,  Chien-I Kuo ,  Li-Li Su ,  Chien-Chang Su ,  Heng-Wen Ting ,  Jung-Chi Tai ,  Che-Hui Lee ,  Ying-Wei Li

IPC: H01L29/66 ,  H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/24 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L21/764 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/1608 ,  H01L29/24 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7853

Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

公开(公告)号：US11652105B2

公开(公告)日：2023-05-16

申请号：US17143681

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chi Tai ,  Yi-Fang Pai ,  Tsz-Mei Kwok ,  Tsung-Hsi Yang ,  Jeng-Wei Yu ,  Cheng-Hsiung Yen ,  Jui-Hsuan Chen ,  Chii-Horng Li ,  Yee-Chia Yeo ,  Heng-Wen Ting ,  Ming-Hua Yu

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

公开(公告)号：US20220376049A1

公开(公告)日：2022-11-24

申请号：US17875644

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yun Chin ,  Chii-Horng Li ,  Chien-Wei Lee ,  Hsueh-Chang Sung ,  Heng-Wen Ting ,  Roger Tai ,  Pei-Ren Jeng ,  Tzu-Hsiang Hsu ,  Yen-Ru Lee ,  Yan-Ting Lin ,  Davie Liu

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.

公开(公告)号：US20220059655A1

公开(公告)日：2022-02-24

申请号：US17520983

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Heng-Wen Ting ,  Kei-Wei Chen ,  Chii-Horng Li ,  Pei-Ren Jeng ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Chun-An Lin

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.