公开(公告)号：US20160020219A1

公开(公告)日：2016-01-21

申请号：US14332556

申请日：2014-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Kai-Shyang You

IPC: H01L27/115 ,  H01L29/423 ,  H01L21/265 ,  H01L29/06 ,  H01L29/49 ,  H01L21/28 ,  H01L27/12 ,  H01L29/51

CPC classification number: H01L21/265 ,  H01L21/26513 ,  H01L21/28017 ,  H01L21/28282 ,  H01L27/11573 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/42344 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/792

Abstract: Some embodiments of the present disclosure provide an integrated circuit arranged on a silicon-on-insulator (SOI) substrate region. The SOI substrate region is made up of a handle wafer region, an oxide layer arranged over the handle wafer region, and a silicon layer arranged over the oxide layer. A recess extends downward from an upper surface of the silicon layer and terminates in the handle wafer region, thereby defining a recessed handle wafer surface and sidewalls extending upwardly from the recessed handle wafer surface to meet the upper surface of the silicon layer. A first semiconductor device is disposed on the recessed handle wafer surface. A second semiconductor device is disposed on the upper surface of the silicon layer.

Abstract translation: 本公开的一些实施例提供了布置在绝缘体上硅（SOI）衬底区域上的集成电路。 SOI衬底区域由处理晶片区域，布置在处理晶片区域上的氧化物层和布置在氧化物层上的硅层构成。 凹部从硅层的上表面向下延伸并且终止于处理晶片区域，从而限定凹入的处理晶片表面和从凹入的处理晶片表面向上延伸以与硅层的上表面相遇的侧壁。 第一半导体器件设置在凹入的处理晶片表面上。 第二半导体器件设置在硅层的上表面上。

公开(公告)号：US09543153B2

公开(公告)日：2017-01-10

申请号：US14332556

申请日：2014-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Kai-Shyang You

IPC: H01L21/265 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/06 ,  H01L29/49 ,  H01L21/28 ,  H01L27/12

CPC classification number: H01L21/265 ,  H01L21/26513 ,  H01L21/28017 ,  H01L21/28282 ,  H01L27/11573 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/42344 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/792

Abstract: An integrated circuit arranged on a silicon-on-insulator (SOI) substrate region is provided. The SOI substrate region is made up of a handle wafer region, an oxide layer arranged over the handle wafer region, and a silicon layer arranged over the oxide layer. A recess extends downward from an upper surface of the silicon layer and terminates in the handle wafer region, thereby defining a recessed handle wafer surface and sidewalls extending upwardly from the recessed handle wafer surface to meet the upper surface of the silicon layer. A first semiconductor device is disposed on the recessed handle wafer surface. A second semiconductor device is disposed on the upper surface of the silicon layer.

Abstract translation: 提供了布置在绝缘体上硅（SOI））衬底区域上的集成电路。 SOI衬底区域由处理晶片区域，布置在处理晶片区域上的氧化物层和布置在氧化物层上的硅层构成。 凹部从硅层的上表面向下延伸并且终止于处理晶片区域，从而限定凹入的处理晶片表面和从凹入的处理晶片表面向上延伸以与硅层的上表面相遇的侧壁。 第一半导体器件设置在凹入的处理晶片表面上。 第二半导体器件设置在硅层的上表面上。