公开(公告)号：US11849655B2

公开(公告)日：2023-12-19

申请号：US17383726

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Shao-Ming Yu ,  Kai-Tai Chang

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/8418 ,  H10B63/24 ,  H10N70/011

Abstract: A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.

公开(公告)号：US20230352551A1

公开(公告)日：2023-11-02

申请号：US18220397

申请日：2023-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Kai-Tai Chang ,  Meng-Hsuan Hsiao

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L29/42392 ,  H01L21/823431 ,  H01L29/66287 ,  H01L21/02433 ,  H01L29/66553 ,  H01L21/823864

Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.

公开(公告)号：US11742405B2

公开(公告)日：2023-08-29

申请号：US17346378

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Kai-Tai Chang ,  Meng-Hsuan Hsiao

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L29/42392 ,  H01L21/02433 ,  H01L21/823431 ,  H01L21/823864 ,  H01L29/66287 ,  H01L29/66553

Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.

公开(公告)号：US20250126842A1

公开(公告)日：2025-04-17

申请号：US18986965

申请日：2024-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Kai-Tai Chang ,  Meng-Hsuan Hsiao

IPC: H10D30/67 ,  H01L21/02 ,  H10D10/01 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03

Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.

公开(公告)号：US20240395766A1

公开(公告)日：2024-11-28

申请号：US18790495

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Tai Chang ,  Tung Ying Lee

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/67 ,  H01L21/68 ,  H01L23/544

Abstract: A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.

公开(公告)号：US11605562B2

公开(公告)日：2023-03-14

申请号：US17141126

申请日：2021-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying Lee ,  Tzu-Chung Wang ,  Kai-Tai Chang ,  Wei-Sheng Yun

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L29/04 ,  H01L29/78

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a plurality of fins on a substrate. A fin end spacer is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. A gate electrode layer is formed on the insulating layer and wrapping around the each channel region. Sidewall spacers are formed on the gate electrode layer.

公开(公告)号：US20210305390A1

公开(公告)日：2021-09-30

申请号：US17346378

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Kai-Tai Chang ,  Meng-Hsuan Hsiao

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.

公开(公告)号：US11038036B2

公开(公告)日：2021-06-15

申请号：US16536113

申请日：2019-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Kai-Tai Chang ,  Meng-Hsuan Hsiao

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.

公开(公告)号：US20220302078A1

公开(公告)日：2022-09-22

申请号：US17369146

申请日：2021-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Tai Chang ,  Tung Ying Lee

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/68 ,  H01L23/544

Abstract: A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.

公开(公告)号：US20200098879A1

公开(公告)日：2020-03-26

申请号：US16536113

申请日：2019-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Kai-Tai Chang ,  Meng-Hsuan Hsiao

IPC: H01L29/423 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66

Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.