公开(公告)号：US11664793B2

公开(公告)日：2023-05-30

申请号：US17571227

申请日：2022-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Hsuan Chou ,  Ya-Tin Chang ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

IPC: H03K5/14 ,  H03L7/089 ,  H03K5/135 ,  H03K5/00

CPC classification number: H03K5/14 ,  H03K5/135 ,  H03L7/0891 ,  H03K2005/00104

Abstract: A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.

公开(公告)号：US11228304B2

公开(公告)日：2022-01-18

申请号：US16952630

申请日：2020-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Hsuan Chou ,  Ya-Tin Chang ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

IPC: H03K5/14 ,  H03K5/135 ,  H03K5/00 ,  H03L7/089

Abstract: A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period, a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.

公开(公告)号：US10928447B2

公开(公告)日：2021-02-23

申请号：US16575275

申请日：2019-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Hsuan Chou ,  Ya-Tin Chang ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

IPC: G01R31/317 ,  H03L7/18 ,  H03L7/085

Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (ΔΣ) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ΔΣ TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ΔΣ TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ΔΣ TDC, wherein the MASH type high-order ΔΣ TDC is configured to measure the phase noise of a device under text (DUT).

公开(公告)号：US11555851B2

公开(公告)日：2023-01-17

申请号：US17736904

申请日：2022-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Hsuan Chou ,  Ya-Tin Chang ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

IPC: G01R31/317 ,  H03L7/18 ,  H03L7/085

Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (ΔΣ) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ΔΣ TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ΔΣ TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ΔΣ TDC, wherein the MASH type high-order ΔΣ TDC is configured to measure the phase noise of a device under text (DUT).

公开(公告)号：US11333708B2

公开(公告)日：2022-05-17

申请号：US17180420

申请日：2021-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Hsuan Chou ,  Ya-Tin Chang ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

IPC: G01R31/317 ,  H03L7/18 ,  H03L7/085

Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (ΔΣ) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ΔΣ TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ΔΣ TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ΔΣ TDC, wherein the MASH type high-order ΔΣ TDC is configured to measure the phase noise of a device under text (DUT).