公开(公告)号：US20210098369A1

公开(公告)日：2021-04-01

申请号：US16943591

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao Kuang ,  Tung-Heng Hsieh ,  Sheng-Hsiung Wang ,  Bao-Ru Young ,  Wang-Jung Hsueh ,  Pang-Chi Wu

IPC: H01L23/522 ,  G06F30/3953 ,  G06F30/392 ,  G06F30/398

Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC design layout defining a semiconductor structure having a via rail extending lengthwise in a first direction and contacting a source contact extending lengthwise in a second direction perpendicular to the first direction. The method further includes identifying the via rail, the source contact, a drain contact being distanced away from the source contact, and a gate structure interposing the source and drain contacts using pattern recognition on the IC design layout. The method further includes determining a position, length, and width of a jog via to be added to the IC design layout. The method further includes adding the jog via having the pre-determined length and width to the IC design layout at the pre-determined position to provide a modified IC design layout and generating a tape-out for fabricating a modified mask.

公开(公告)号：US20230326804A1

公开(公告)日：2023-10-12

申请号：US18335806

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chieh Wu ,  Pang-Chi Wu ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Hsien-Huang Liao ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/66545 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/76805

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

公开(公告)号：US20250149439A1

公开(公告)日：2025-05-08

申请号：US19018736

申请日：2025-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao Kuang ,  Tung-Heng Hsieh ,  Sheng-Hsiung Wang ,  Bao-Ru Young ,  Wang-Jung Hsueh ,  Pang-Chi Wu

IPC: H01L23/522 ,  G06F30/392 ,  G06F30/3953 ,  G06F30/398

Abstract: A device includes a semiconductor substrate, an active region over the semiconductor substrate extending lengthwise in a first direction, a gate structure over the active region extending lengthwise in a second direction perpendicular to the first direction, a source feature and a drain feature on the active region and interposed by the gate structure, a source contact on the source feature, a drain contact on the drain feature, and a via rail over the substrate spaced from the active region. The via rail includes a main portion extending lengthwise in the first direction having a sidewall surface facing opposite the end surface of the drain contact, and a jog via extending from the main portion along the second direction and having a sidewall surface facing the second direction, each of the main portion and the jog via contacting the source contact.

公开(公告)号：US12068201B2

公开(公告)日：2024-08-20

申请号：US18335806

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chieh Wu ,  Pang-Chi Wu ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Hsien-Huang Liao ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L21/82 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/66545

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

公开(公告)号：US12199034B2

公开(公告)日：2025-01-14

申请号：US18454209

申请日：2023-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao Kuang ,  Tung-Heng Hsieh ,  Sheng-Hsiung Wang ,  Bao-Ru Young ,  Wang-Jung Hsueh ,  Pang-Chi Wu

IPC: H01L23/522 ,  G06F30/392 ,  G06F30/3953 ,  G06F30/398

Abstract: A device includes a semiconductor substrate, an active region over the semiconductor substrate extending lengthwise in a first direction, a gate structure over the active region extending lengthwise in a second direction perpendicular to the first direction, a source feature and a drain feature on the active region and interposed by the gate structure, a source contact on the source feature, a drain contact on the drain feature, and a via rail over the substrate spaced from the active region. The via rail includes a main portion extending lengthwise in the first direction having a sidewall surface facing opposite the end surface of the drain contact, and a jog via extending from the main portion along the second direction and having a sidewall surface facing the second direction, each of the main portion and the jog via contacting the source contact.

公开(公告)号：US20240363427A1

公开(公告)日：2024-10-31

申请号：US18764973

申请日：2024-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chieh Wu ,  Pang-Chi Wu ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Hsien-Huang Liao ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L21/8234 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/66545

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

公开(公告)号：US20230411280A1

公开(公告)日：2023-12-21

申请号：US18454209

申请日：2023-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao Kuang ,  Tung-Heng Hsieh ,  Sheng-Hsiung Wang ,  Bao-Ru Young ,  Wang-Jung Hsueh ,  Pang-Chi Wu

IPC: H01L23/522 ,  G06F30/398 ,  G06F30/392 ,  G06F30/3953

CPC classification number: H01L23/5226 ,  G06F30/3953 ,  G06F30/392 ,  G06F30/398

Abstract: A device includes a semiconductor substrate, an active region over the semiconductor substrate extending lengthwise in a first direction, a gate structure over the active region extending lengthwise in a second direction perpendicular to the first direction, a source feature and a drain feature on the active region and interposed by the gate structure, a source contact on the source feature, a drain contact on the drain feature, and a via rail over the substrate spaced from the active region. The via rail includes a main portion extending lengthwise in the first direction having a sidewall surface facing opposite the end surface of the drain contact, and a jog via extending from the main portion along the second direction and having a sidewall surface facing the second direction, each of the main portion and the jog via contacting the source contact.