公开(公告)号：US20250149439A1

公开(公告)日：2025-05-08

申请号：US19018736

申请日：2025-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao Kuang ,  Tung-Heng Hsieh ,  Sheng-Hsiung Wang ,  Bao-Ru Young ,  Wang-Jung Hsueh ,  Pang-Chi Wu

IPC: H01L23/522 ,  G06F30/392 ,  G06F30/3953 ,  G06F30/398

Abstract: A device includes a semiconductor substrate, an active region over the semiconductor substrate extending lengthwise in a first direction, a gate structure over the active region extending lengthwise in a second direction perpendicular to the first direction, a source feature and a drain feature on the active region and interposed by the gate structure, a source contact on the source feature, a drain contact on the drain feature, and a via rail over the substrate spaced from the active region. The via rail includes a main portion extending lengthwise in the first direction having a sidewall surface facing opposite the end surface of the drain contact, and a jog via extending from the main portion along the second direction and having a sidewall surface facing the second direction, each of the main portion and the jog via contacting the source contact.

公开(公告)号：US12288784B2

公开(公告)日：2025-04-29

申请号：US18361701

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung Feng Chang ,  Chun-Chia Hsu ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/08

Abstract: A semiconductor structure includes a substrate having a first well of a first conductivity type and a second well of a second conductivity type. From a top view, the first well includes first and seconds edges extending along a first direction. The second edge has multiple turns, resulting in the first well having a protruding section and a recessed section. The semiconductor structure further includes a first source/drain feature over the protruding section and a second source/drain feature over a main body of the first well. The first source/drain feature is of the first conductivity type. The second source/drain feature is of the second conductivity type. The first and the second source/drain features are generally aligned along a second direction perpendicular to the first direction from the top view.

公开(公告)号：US12068201B2

公开(公告)日：2024-08-20

申请号：US18335806

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chieh Wu ,  Pang-Chi Wu ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Hsien-Huang Liao ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L21/82 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/66545

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

公开(公告)号：US20240213099A1

公开(公告)日：2024-06-27

申请号：US18601074

申请日：2024-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhe-Ching Lu ,  Yen-Sen Wang ,  Bao-Ru Young ,  Tsung-Chieh Tsai

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first semiconductor layer including a first semiconductor material in a first area of a substrate; alternately depositing second semiconductor layers and third semiconductor layers over the first semiconductor layer and over the substrate to form a semiconductor layer stack, wherein the second semiconductor layers include a second semiconductor material, the third semiconductor layers include the first semiconductor material, the second semiconductor material is different from the first semiconductor material, and a bottom surface of one of the second semiconductor layers contacts the first semiconductor layer in the first area and contacts the substrate in a second area of the substrate; planarizing a top surface of the semiconductor layer stack; and patterning the semiconductor layer stack to form a first semiconductor structure in the first area and a second semiconductor structure in the second area.

公开(公告)号：US11798942B2

公开(公告)日：2023-10-24

申请号：US17240673

申请日：2021-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Sheng Fan ,  Bao-Ru Young ,  Tung-Heng Hsieh

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/823828 ,  H01L21/823878

Abstract: A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.

公开(公告)号：US11581221B2

公开(公告)日：2023-02-14

申请号：US17106639

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hsiung Wang ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L21/768 ,  G06F30/39 ,  G06F30/398 ,  H01L21/66 ,  H01L23/50 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/118 ,  G06F119/18

Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having active regions, conductive contact features landing on the active regions, and a conductive via feature to be landing on a first subset of the conductive contact features and to be spaced from a second subset of the conductive contact features; evaluating a spatial parameter of the conductive via feature to the conductive contact features; and modifying the IC layout according to the spatial parameter such that the conductive via feature has a S-curved shape.

公开(公告)号：US11527527B2

公开(公告)日：2022-12-13

申请号：US16880939

申请日：2020-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Feng Chang ,  Bao-Ru Young ,  Tung-Heng Hsieh ,  Chun-Chia Hsu

IPC: H01L27/02 ,  H01L21/82 ,  G06F30/392 ,  H01L27/092 ,  H01L21/8238

Abstract: Provided is a tap cell including a substrate, a first well, a second well, a first doped region, and the second doped region. The substrate has a first region and a second region. The first well has a first dopant type and includes a first portion disposed in the first region and a second portion extending into the second region. The second well has a second dopant type and includes a third portion disposed in the second region and a fourth portion extending into the first region. The first doped region having the first dopant type is disposed in the second portion of the first well and the third portion of the second well along the second region. The second doped region having the second dopant type is disposed in the first portion of the first well and the fourth portion of the second well along the first region.

公开(公告)号：US20220352341A1

公开(公告)日：2022-11-03

申请号：US17813700

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jyun HUANG ,  Bao-Ru Young ,  Tung-Heng Hsieh

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

Abstract: The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.

公开(公告)号：US20210366895A1

公开(公告)日：2021-11-25

申请号：US16880939

申请日：2020-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Feng Chang ,  Bao-Ru Young ,  Tung-Heng Hsieh ,  Chun-Chia Hsu

IPC: H01L27/02 ,  G06F30/392 ,  H01L21/82

Abstract: Provided is a tap cell including a substrate, a first well, a second well, a first doped region, and the second doped region. The substrate has a first region and a second region. The first well has a first dopant type and includes a first portion disposed in the first region and a second portion extending into the second region. The second well has a second dopant type and includes a third portion disposed in the second region and a fourth portion extending into the first region. The first doped region having the first dopant type is disposed in the second portion of the first well and the third portion of the second well along the second region. The second doped region having the second dopant type is disposed in the first portion of the first well and the fourth portion of the second well along the first region.

公开(公告)号：US11004842B2

公开(公告)日：2021-05-11

申请号：US16658389

申请日：2019-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Chi Lee ,  Tung-Heng Hsieh ,  Bao-Ru Young ,  Yung Feng Chang

IPC: H01L29/08 ,  H01L27/02 ,  H01L29/66 ,  H01L21/266 ,  H01L21/3115 ,  H01L29/78 ,  H01L29/06 ,  G06F30/392

Abstract: A mandrel is formed over an active region that includes a first region and a second region. The first region and the second region are reserved for the formation of a source and a drain of a FinFET, respectively. A portion of the mandrel formed over the second region is broken up into a first segment and a second segment separated from the first segment by a gap. Spacers are formed on opposite sides of the mandrel. Using the spacers, fins are defined. The fins protrude upwardly out of the active region. A portion of the second region corresponding to the gap has no fins formed thereover. The source is epitaxially grown on the fins in the first region. At least a portion of the drain is epitaxially grown on the portion of the second region having no fins.