公开(公告)号：US20240363427A1

公开(公告)日：2024-10-31

申请号：US18764973

申请日：2024-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chieh Wu ,  Pang-Chi Wu ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Hsien-Huang Liao ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L21/8234 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/66545

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

公开(公告)号：US20250081523A1

公开(公告)日：2025-03-06

申请号：US18239283

申请日：2023-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Ming Lee ,  Shih-Chieh Wu ,  Po-Yu Huang ,  I-Wen Wu ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/417 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor die and the method of forming the same are provided. The semiconductor die includes a first interconnect structure, a second interconnect structure including a conductive feature, and a device layer between the first interconnect structure and the second interconnect structure. The device layer includes a semiconductor fin, a first gate structure on the semiconductor fin, a source/drain region adjacent the first gate structure, and a shared contact extending through the semiconductor fin to be electrically connected to the source/drain region and the first gate structure. The conductive feature contacts the shared contact.

公开(公告)号：US20230326804A1

公开(公告)日：2023-10-12

申请号：US18335806

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chieh Wu ,  Pang-Chi Wu ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Hsien-Huang Liao ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/66545 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/76805

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

公开(公告)号：US12068201B2

公开(公告)日：2024-08-20

申请号：US18335806

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chieh Wu ,  Pang-Chi Wu ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Hsien-Huang Liao ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L21/82 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/66545

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.