公开(公告)号：US20230063463A1

公开(公告)日：2023-03-02

申请号：US17462350

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Po-Shao Lin ,  Wei-Yang Lee

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/78

Abstract: Semiconductor devices and methods of fabrication are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin and into a substrate as an initial step in forming a source/drain region. A first semiconductor material is epitaxially grown from channels exposed along sidewalls of the opening to form first source/drain structures. A second semiconductor material is epitaxially grown from the first semiconductor material to form a second source/drain structure over and to fill a space between the first source/drain structures. A bottom of the second source/drain structure is located below a bottommost surface of the first source/drain structures. The second semiconductor material has a greater concentration percentage by volume of germanium than the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.

公开(公告)号：US20240153993A1

公开(公告)日：2024-05-09

申请号：US18415281

申请日：2024-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Po-Shao Lin ,  Wei-Yang Lee

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851

Abstract: Semiconductor devices and methods of fabrication are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin and into a substrate as an initial step in forming a source/drain region. A first semiconductor material is epitaxially grown from channels exposed along sidewalls of the opening to form first source/drain structures. A second semiconductor material is epitaxially grown from the first semiconductor material to form a second source/drain structure over and to fill a space between the first source/drain structures. A bottom of the second source/drain structure is located below a bottommost surface of the first source/drain structures. The second semiconductor material has a greater concentration percentage by volume of germanium than the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.

公开(公告)号：US11901410B2

公开(公告)日：2024-02-13

申请号：US17462350

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Po-Shao Lin ,  Wei-Yang Lee

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851

Abstract: Semiconductor devices and methods of fabrication are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin and into a substrate as an initial step in forming a source/drain region. A first semiconductor material is epitaxially grown from channels exposed along sidewalls of the opening to form first source/drain structures. A second semiconductor material is epitaxially grown from the first semiconductor material to form a second source/drain structure over and to fill a space between the first source/drain structures. A bottom of the second source/drain structure is located below a bottommost surface of the first source/drain structures. The second semiconductor material has a greater concentration percentage by volume of germanium than the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.