公开(公告)号：US12266655B2

公开(公告)日：2025-04-01

申请号：US17657833

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Bo-Yu Lai ,  Chien-Wei Lee ,  Hsueh-Chang Sung ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.

公开(公告)号：US20230088288A1

公开(公告)日：2023-03-23

申请号：US17991560

申请日：2022-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiu Liu ,  Feng-Cheng Yang ,  Tsung-Lin Lee ,  Wei-Yang Lee ,  Yen-Ming Chen ,  Yen-Ting Chen

IPC: H01L29/51 ,  H01L27/088 ,  H01L21/311 ,  H01L29/66

Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.

公开(公告)号：US20220352038A1

公开(公告)日：2022-11-03

申请号：US17813086

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L21/768 ,  H01L21/311 ,  H01L29/08 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092

Abstract: A semiconductor device and methods of forming the semiconductor device are described herein and are directed towards forming a source/drain contact plug for adjacent finFETs. The source/drain regions of the adjacent finFETs are embedded in an interlayer dielectric and are separated by an isolation region of a cut-metal gate (CMG) structure isolating gate electrodes of the adjacent finFETs The methods include recessing the isolation region, forming a contact plug opening through the interlayer dielectric to expose portions of a contact etch stop layer disposed over the source/drain regions through the contact plug opening, the contact etch stop layer being a different material from the material of the isolation region. Once exposed, the portions of the CESL are removed and a conductive material is formed in the contact plug opening and in contact with the source/drain regions of the adjacent finFETs and in contact with the isolation region.

公开(公告)号：US11446785B2

公开(公告)日：2022-09-20

申请号：US16584874

申请日：2019-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Chieh Chang ,  Yen-Ting Chen ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: B24B53/017 ,  B24B37/20

Abstract: Provided herein are chemical-mechanical planarization (CMP) systems and methods to reduce metal particle pollution on dressing disks and polishing pads. Such methods may include contacting a dressing disk and at least one conductive element with an electrolyte solution and applying direct current (DC) power to the dressing disk and the at least one conductive element.

公开(公告)号：US20210111265A1

公开(公告)日：2021-04-15

申请号：US17107343

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/78

Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.

公开(公告)号：US20200075420A1

公开(公告)日：2020-03-05

申请号：US16678472

申请日：2019-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/768

Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.

公开(公告)号：US12087590B2

公开(公告)日：2024-09-10

申请号：US18066934

申请日：2022-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Kung ,  Hui-Chi Huang ,  Kei-Wei Chen ,  Yen-Ting Chen

IPC: H01L21/306 ,  B24B37/24 ,  H01L21/321

CPC classification number: H01L21/30625 ,  B24B37/24 ,  H01L21/3212

Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.

公开(公告)号：US20230118617A1

公开(公告)日：2023-04-20

申请号：US18066934

申请日：2022-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Kung ,  Hui-Chi Huang ,  Kei-Wei Chen ,  Yen-Ting Chen

IPC: H01L21/306 ,  B24B37/24 ,  H01L21/321

Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.

公开(公告)号：US20220130730A1

公开(公告)日：2022-04-28

申请号：US17567309

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Yang ,  Feng-Cheng Yang ,  Wei-Yang Lee ,  Yen-Ming Chen ,  Yen-Ting Chen

IPC: H01L21/8234 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/308 ,  H01L21/762

Abstract: A semiconductor device including a fin field effect transistor (FinFET) with a cut metal gate (CMG) and a method of manufacturing the semiconductor device are described herein. The method includes forming a CMG protective helmet structure at a top portion of a CMG dummy gate plug formed within a semiconductor substrate. The CMG protective helmet structure prevents consumption and damage of a dummy filler material in a CMG region and prevents undesirable polymer/residue byproducts from forming on top surfaces of epitaxial regions of the FinFET during etching processes.

公开(公告)号：US10978350B2

公开(公告)日：2021-04-13

申请号：US16698336

申请日：2019-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Chia-Lin Hsu

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/20 ,  H01L21/28 ,  H01L21/02 ,  H01L21/283 ,  H01L29/51 ,  H01L29/06 ,  H01L23/532 ,  H01L29/49 ,  H01L29/78 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

Abstract: Metal gate formation methods are disclosed herein for providing metal gates with low work function to enhance semiconductor field effect transistor performance. An exemplary method includes forming a gate dielectric layer on a substrate and a barrier layer over the gate dielectric layer. An outer surface of the barrier layer is treated to increase its roughness. After the outer surface of the barrier layer is roughened, a metal layer is deposited over the barrier layer.