公开(公告)号：US11690228B2

公开(公告)日：2023-06-27

申请号：US17184892

申请日：2021-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Song-Fu Liao ,  Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L21/02 ,  H10B51/30 ,  H01L21/768 ,  H10B53/30

CPC classification number: H10B51/30 ,  H01L21/76876 ,  H10B53/30

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.

公开(公告)号：US20220271047A1

公开(公告)日：2022-08-25

申请号：US17184892

申请日：2021-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Song-Fu Liao ,  Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L27/1159 ,  H01L27/11507 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.