公开(公告)号：US11417539B2

公开(公告)日：2022-08-16

申请号：US17085346

申请日：2020-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Hsiung Lu ,  Ming-Da Cheng ,  Su-Fei Lin ,  Hsu-Lun Liu ,  Chien-Pin Chan ,  Yung-Sheng Lin

IPC: H01L21/48 ,  C25D5/00 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538

Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

公开(公告)号：US20230154880A1

公开(公告)日：2023-05-18

申请号：US18151014

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Hsu-Lun Liu ,  Kai-Di Wu ,  Su-Fei Lin

IPC: H01L23/00

CPC classification number: H01L24/20 ,  H01L24/19 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/2101

Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

公开(公告)号：US20240387433A1

公开(公告)日：2024-11-21

申请号：US18782141

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Po-Hao Tsai ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Hsu-Lun Liu ,  Kai-Di Wu ,  Su-Fei Lin

IPC: H01L23/00

Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

公开(公告)号：US11594508B2

公开(公告)日：2023-02-28

申请号：US17069539

申请日：2020-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Hsu-Lun Liu ,  Kai-Di Wu ,  Su-Fei Lin

IPC: H01L23/00

Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

公开(公告)号：US20210375815A1

公开(公告)日：2021-12-02

申请号：US17069539

申请日：2020-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Hsu-Lun Liu ,  Kai-Di Wu ,  Su-Fei Lin

IPC: H01L23/00

Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.