公开(公告)号：US12176347B2

公开(公告)日：2024-12-24

申请号：US18349486

申请日：2023-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor in a first area and a second transistor in a second area. The first transistor includes a first gate structure extending lengthwise along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer over sidewalls of the first gate structure. The second transistor includes a second gate structure extending lengthwise along the first direction, and the first gate spacer and the third gate spacer over sidewalls of the second gate structure. The first gate spacer, the second gate spacer and the third gate spacer are of different compositions and the third gate spacer is directly on the first gate spacer in the second area.

公开(公告)号：US20220238729A1

公开(公告)日：2022-07-28

申请号：US17159289

申请日：2021-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L29/94 ,  H01L27/06 ,  H01L29/78 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards a FinFET MOS capacitor. In some embodiments, the FinFET MOS capacitor comprises a substrate and a capacitor fin structure extending upwardly from an upper surface of the substrate. The capacitor fin structure comprises a pair of dummy source/drain regions separated by a dummy channel region and a capacitor gate structure straddling on the capacitor fin structure. The capacitor gate structure is separated from the capacitor fin structure by a capacitor gate dielectric.

公开(公告)号：US12224213B2

公开(公告)日：2025-02-11

申请号：US17008251

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/308 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H03M1/06

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.

公开(公告)号：US20220359304A1

公开(公告)日：2022-11-10

申请号：US17874503

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L21/8234 ,  H01L27/088

Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a substrate including a core device region and an input/output (I/O) device region, a plurality of core devices in the core device region, each of the plurality of core devices including a first active region extending along a first direction, and a first plurality of input/output (I/O) transistors in the I/O device region, each of the first plurality of I/O transistors including a second active region extending along the first direction. The first active region includes a first width along a second direction perpendicular to the first direction and the second active region includes a second width along the second direction. The second width is greater than the first width.

公开(公告)号：US11444175B2

公开(公告)日：2022-09-13

申请号：US17008045

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3213

Abstract: Semiconductor devices and methods of forming the same are provided. An example method includes providing a workpiece including a first dummy gate stack and a second dummy gate stack in a first area of the workpiece, a third dummy gate stack and a fourth dummy gate stack in a second area of the workpiece, a hard mask layer over each of the first dummy gate stack, the second dummy gate stack, the third dummy gate stack, and the fourth dummy gate stack. The method further includes depositing a photoresist (PR) layer over the workpiece to form a first PR layer portion over the first area and a second PR layer portion over the second area; and selectively forming a first opening through the second PR layer portion over the third dummy gate stack and a second opening through the second PR layer portion over the fourth dummy gate stack.

公开(公告)号：US20220068721A1

公开(公告)日：2022-03-03

申请号：US17008251

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L21/8234 ,  H01L27/088

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.

公开(公告)号：US20210335784A1

公开(公告)日：2021-10-28

申请号：US17025802

申请日：2020-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor in a first area and a second transistor in a second area. The first transistor includes a first gate structure extending lengthwise along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer over sidewalls of the first gate structure. The second transistor includes a second gate structure extending lengthwise along the first direction, and the first gate spacer and the third gate spacer over sidewalls of the second gate structure. The first gate spacer, the second gate spacer and the third gate spacer are of different compositions and the third gate spacer is directly on the first gate spacer in the second area.

公开(公告)号：US20240387284A1

公开(公告)日：2024-11-21

申请号：US18787740

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/308 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H03M1/06

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.

公开(公告)号：US11855175B2

公开(公告)日：2023-12-26

申请号：US17813652

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66484 ,  H01L21/32139 ,  H01L21/82385 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/7855

Abstract: Semiconductor devices and methods of forming the same are provided. An example method includes providing a workpiece including a first dummy gate stack and a second dummy gate stack in a first area of the workpiece, a third dummy gate stack and a fourth dummy gate stack in a second area of the workpiece, a hard mask layer over each of the first dummy gate stack, the second dummy gate stack, the third dummy gate stack, and the fourth dummy gate stack. The method further includes depositing a photoresist (PR) layer over the workpiece to form a first PR layer portion over the first area and a second PR layer portion over the second area; and selectively forming a first opening through the second PR layer portion over the third dummy gate stack and a second opening through the second PR layer portion over the fourth dummy gate stack.

公开(公告)号：US20230352483A1

公开(公告)日：2023-11-02

申请号：US18349486

申请日：2023-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L29/6681 ,  H01L21/823468 ,  H01L29/785 ,  H01L21/823431 ,  H01L29/41791

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor in a first area and a second transistor in a second area. The first transistor includes a first gate structure extending lengthwise along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer over sidewalls of the first gate structure. The second transistor includes a second gate structure extending lengthwise along the first direction, and the first gate spacer and the third gate spacer over sidewalls of the second gate structure. The first gate spacer, the second gate spacer and the third gate spacer are of different compositions and the third gate spacer is directly on the first gate spacer in the second area.