公开(公告)号：US20170122998A1

公开(公告)日：2017-05-04

申请号：US14926434

申请日：2015-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yu Liu ,  Cheng Hsiao ,  Chia-Yi Chen ,  Wen-Cheng Huang ,  Ke-Wei Su ,  Ke-Ying Su ,  Ping-Hung Yuh

IPC: G01R31/28

CPC classification number: G06F17/50 ,  G01R31/28 ,  G01R31/2856 ,  G06F17/5031 ,  G06F17/5077

Abstract: A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.

公开(公告)号：US20140282341A1

公开(公告)日：2014-09-18

申请号：US13906614

申请日：2013-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ming Ho ,  Te-Yu Liu ,  Austin Chingyu Chiang ,  Meng-Fan Wu ,  Ke-Ying Su

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: The present disclosure relates to a method of RC extraction that provides for a fast development time and easy maintenance. In some embodiments, the method provides a graphical representation of an integrated chip layout having a plurality of integrated chip components. A plurality of pattern based graphical features are then determined. Respective pattern based graphical features define a structural aspect of an integrated chip component. One of the plurality of integrated chip components is defined as a pattern oriented function having inputs of one or more of the pattern based graphical features. The pattern oriented function determines a shape of the one of the plurality of integrated chip components based upon a relation between the plurality of inputs. By determining a shape of an integrated chip component using a pattern oriented function, the complexity of RC profiles can be reduced.

Abstract translation: 本公开涉及一种提供快速开发时间和易于维护的RC提取方法。 在一些实施例中，该方法提供具有多个集成芯片组件的集成芯片布局的图形表示。 然后确定多个基于图案的图形特征。 基于图案的图形特征定义了集成芯片组件的结构方面。 多个集成芯片组件中的一个被定义为具有基于图案的图形特征中的一个或多个的输入的具有图案的功能。 基于图案的功能基于多个输入之间的关系确定多个集成芯片组件中的一个的形状。 通过使用面向图案的功能确定集成芯片组件的形状，可以减小RC轮廓的复杂性。

公开(公告)号：US08887116B2

公开(公告)日：2014-11-11

申请号：US13906614

申请日：2013-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ming Ho ,  Te-Yu Liu ,  Austin Chingyu Chiang ,  Meng-Fan Wu ,  Ke-Ying Su

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: The present disclosure relates to a method of RC extraction that provides for a fast development time and easy maintenance. In some embodiments, the method provides a graphical representation of an integrated chip layout having a plurality of integrated chip components. A plurality of pattern based graphical features are then determined. Respective pattern based graphical features define a structural aspect of an integrated chip component. One of the plurality of integrated chip components is defined as a pattern oriented function having inputs of one or more of the pattern based graphical features. The pattern oriented function determines a shape of the one of the plurality of integrated chip components based upon a relation between the plurality of inputs. By determining a shape of an integrated chip component using a pattern oriented function, the complexity of RC profiles can be reduced.

Abstract translation: 本公开涉及一种提供快速开发时间和易于维护的RC提取方法。 在一些实施例中，该方法提供具有多个集成芯片组件的集成芯片布局的图形表示。 然后确定多个基于图案的图形特征。 基于图案的图形特征定义了集成芯片组件的结构方面。 多个集成芯片组件中的一个被定义为具有基于图案的图形特征中的一个或多个的输入的具有图案的功能。 基于图案的功能基于多个输入之间的关系确定多个集成芯片组件中的一个的形状。 通过使用面向图案的功能确定集成芯片组件的形状，可以减小RC轮廓的复杂性。

公开(公告)号：US09904743B2

公开(公告)日：2018-02-27

申请号：US14926434

申请日：2015-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yu Liu ,  Cheng Hsiao ,  Chia-Yi Chen ,  Wen-Cheng Huang ,  Ke-Wei Su ,  Ke-Ying Su ,  Ping-Hung Yuh

IPC: G01R31/02 ,  G06F17/50 ,  G01R31/28

CPC classification number: G06F17/50 ,  G01R31/28 ,  G01R31/2856 ,  G06F17/5031 ,  G06F17/5077

Abstract: A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.