公开(公告)号：US20170316138A1

公开(公告)日：2017-11-02

申请号：US15335091

申请日：2016-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine Chiang ,  Cheng Hsiao ,  Chang-Yu Huang ,  Juan Yi Chen ,  Ke-Wei Su ,  Chung-Kai Lin ,  Lester Chang ,  Min-Chie Jeng

IPC: G06F17/50 ,  G06F7/58

Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

公开(公告)号：US10521538B2

公开(公告)日：2019-12-31

申请号：US15335091

申请日：2016-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine Chiang ,  Cheng Hsiao ,  Chang-Yu Huang ,  Juan Yi Chen ,  Ke-Wei Su ,  Chung-Kai Lin ,  Lester Chang ,  Min-Chie Jeng

IPC: H01J37/32 ,  G06F17/50 ,  G06F7/58

Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

公开(公告)号：US20170122998A1

公开(公告)日：2017-05-04

申请号：US14926434

申请日：2015-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yu Liu ,  Cheng Hsiao ,  Chia-Yi Chen ,  Wen-Cheng Huang ,  Ke-Wei Su ,  Ke-Ying Su ,  Ping-Hung Yuh

IPC: G01R31/28

CPC classification number: G06F17/50 ,  G01R31/28 ,  G01R31/2856 ,  G06F17/5031 ,  G06F17/5077

Abstract: A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.

公开(公告)号：US10860769B2

公开(公告)日：2020-12-08

申请号：US16721255

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine Chiang ,  Cheng Hsiao ,  Chang-Yu Huang ,  Juan Yi Chen ,  Ke-Wei Su ,  Chung-Kai Lin ,  Lester Chang ,  Min-Chie Jeng

IPC: G06F30/39 ,  G06F30/367 ,  G06F7/58

Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

公开(公告)号：US09904743B2

公开(公告)日：2018-02-27

申请号：US14926434

申请日：2015-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yu Liu ,  Cheng Hsiao ,  Chia-Yi Chen ,  Wen-Cheng Huang ,  Ke-Wei Su ,  Ke-Ying Su ,  Ping-Hung Yuh

IPC: G01R31/02 ,  G06F17/50 ,  G01R31/28

CPC classification number: G06F17/50 ,  G01R31/28 ,  G01R31/2856 ,  G06F17/5031 ,  G06F17/5077

Abstract: A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.

公开(公告)号：US20200125782A1

公开(公告)日：2020-04-23

申请号：US16721255

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine Chiang ,  Cheng Hsiao ,  Chang-Yu Huang ,  Juan Yi Chen ,  Ke-Wei Su ,  Chung-Kai Lin ,  Lester Chang ,  Min-Chie Jeng

IPC: G06F30/39 ,  G06F7/58 ,  G06F30/367

Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

公开(公告)号：US10216879B1

公开(公告)日：2019-02-26

申请号：US15682863

申请日：2017-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shun Huang ,  Wai-Kit Lee ,  Ya-Chin Liang ,  Cheng Hsiao ,  Juan-Yi Chen ,  Li-Chung Hsu ,  Ting-Sheng Huang ,  Ke-Wei Su ,  Chung-Kai Lin ,  Min-Chie Jeng

IPC: G06F17/50 ,  G06F17/30 ,  H01L21/66

Abstract: A method for establishing an aging model of a device is provided. The device is measured to obtain degradation information of the device under an operating condition, wherein the device is a physical device. The degradation information is partitioned into a permanent degradation portion and an impermanent degradation portion. The impermanent degradation portion is differentiated by time to obtain a differential value. The aging model is obtained according to the differential value. When the differential value is greater than zero, a degradation of the device increases over time, and when the differential value is less than zero, the degradation of the device decreases over time.