公开(公告)号：US20170122998A1

公开(公告)日：2017-05-04

申请号：US14926434

申请日：2015-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yu Liu ,  Cheng Hsiao ,  Chia-Yi Chen ,  Wen-Cheng Huang ,  Ke-Wei Su ,  Ke-Ying Su ,  Ping-Hung Yuh

IPC: G01R31/28

CPC classification number: G06F17/50 ,  G01R31/28 ,  G01R31/2856 ,  G06F17/5031 ,  G06F17/5077

Abstract: A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.

公开(公告)号：US08732628B1

公开(公告)日：2014-05-20

申请号：US13742689

申请日：2013-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Fan Wu ,  I-Fan Lin ,  Ke-Ying Su ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G03F1/70 ,  G03F1/38 ,  G03F7/70466

Abstract: A method comprises: selecting a circuit pattern or network of circuit patterns in a layout of an integrated circuit (IC) to be fabricating using double patterning technology (DPT). Circuit patterns near the selected circuit pattern or network are grouped into one or more groups. For each group, a respective expected resistance-capacitance (RC) extraction error cost is calculated, which is associated with a mask alignment error, for two different sets of mask assignments. The circuit patterns in the one or more groups are assigned to be patterned by respective photomasks, so as to minimize a total of the expected RC extraction error costs.

Abstract translation: 一种方法包括：在使用双重图案化技术（DPT）制造的集成电路（IC）的布局中选择电路图案的电路图案或网络。 所选择的电路图案或网络附近的电路图案被分组成一个或多个组。 对于每个组，对于两组不同的掩模分配，计算与掩模对准误差相关联的相应的预期电阻 - 电容（RC）提取误差成本。 一个或多个组中的电路图案被分配为通过相应的光掩模进行图案化，以便最小化预期RC提取误差成本的总和。

公开(公告)号：US09021412B2

公开(公告)日：2015-04-28

申请号：US14087065

申请日：2013-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ze-Ming Wu ,  Ching-Shun Yang ,  Ke-Ying Su ,  Hsiao-Shu Chao

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5068

Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

Abstract translation: 本公开涉及用于产生用于RC提取的穿硅通孔（TSV）模型的方法和装置，其精确地对包括一个或多个TSV的插入器衬底进行建模。 在一些实施例中，通过产生具有对TSV进行建模的子电路的插入器晶片模型来执行方法。 子电路可以补偿由EDA工具执行的传统TSV模型的电阻和电容提取的限制。 在一些实施例中，子电路耦合到模型的浮动公共节点。 浮动公共节点使得插入器晶片模型能够考虑插入器内的电容耦合。 改进的插入器晶片模型使得能够利用一个或多个TSV对插入件进行精确的RC提取，从而提供在GDS和APR流之间一致的插入器晶片模型。

公开(公告)号：US20140282341A1

公开(公告)日：2014-09-18

申请号：US13906614

申请日：2013-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ming Ho ,  Te-Yu Liu ,  Austin Chingyu Chiang ,  Meng-Fan Wu ,  Ke-Ying Su

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: The present disclosure relates to a method of RC extraction that provides for a fast development time and easy maintenance. In some embodiments, the method provides a graphical representation of an integrated chip layout having a plurality of integrated chip components. A plurality of pattern based graphical features are then determined. Respective pattern based graphical features define a structural aspect of an integrated chip component. One of the plurality of integrated chip components is defined as a pattern oriented function having inputs of one or more of the pattern based graphical features. The pattern oriented function determines a shape of the one of the plurality of integrated chip components based upon a relation between the plurality of inputs. By determining a shape of an integrated chip component using a pattern oriented function, the complexity of RC profiles can be reduced.

Abstract translation: 本公开涉及一种提供快速开发时间和易于维护的RC提取方法。 在一些实施例中，该方法提供具有多个集成芯片组件的集成芯片布局的图形表示。 然后确定多个基于图案的图形特征。 基于图案的图形特征定义了集成芯片组件的结构方面。 多个集成芯片组件中的一个被定义为具有基于图案的图形特征中的一个或多个的输入的具有图案的功能。 基于图案的功能基于多个输入之间的关系确定多个集成芯片组件中的一个的形状。 通过使用面向图案的功能确定集成芯片组件的形状，可以减小RC轮廓的复杂性。

公开(公告)号：US09904743B2

公开(公告)日：2018-02-27

申请号：US14926434

申请日：2015-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yu Liu ,  Cheng Hsiao ,  Chia-Yi Chen ,  Wen-Cheng Huang ,  Ke-Wei Su ,  Ke-Ying Su ,  Ping-Hung Yuh

IPC: G01R31/02 ,  G06F17/50 ,  G01R31/28

CPC classification number: G06F17/50 ,  G01R31/28 ,  G01R31/2856 ,  G06F17/5031 ,  G06F17/5077

Abstract: A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.

公开(公告)号：US08745559B2

公开(公告)日：2014-06-03

申请号：US13872180

申请日：2013-04-29

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Chih-Cheng Chou ,  Ke-Ying Su

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5036 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/12 ,  G06F2217/40

Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die including at least one metal layer to be formed using at least one of a single patterning process or a multi-patterning process, creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the metal layer of at least one die based on the technology file, simulating a performance of the integrated circuit based on the netlist, adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and repeating the simulating and adjusting to optimize the at least one of the capacitive or inductive couplings.

Abstract translation: 一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括至少一个管芯，所述至少一个管芯包括要使用单个图案化工艺或多图案化工艺中的至少一个形成的至少一个金属层，创建包括近似于 基于技术文件，在至少一个管芯的金属层中的导体之间的电容或电感耦合中的至少一个，模拟基于网表的集成电路的性能，基于网络调整至少一个管芯和插入器之间的布线，基于 模拟以减少电容或电感耦合中的至少一个，并且重复模拟和调整以优化电容或电感耦合中的至少一个。

公开(公告)号：US20140082578A1

公开(公告)日：2014-03-20

申请号：US14087065

申请日：2013-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ze-Ming Wu ,  Ching-Shun Yang ,  Ke-Ying Su ,  Hsiao-Shu Chao

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5068

Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

Abstract translation: 本公开涉及用于产生用于RC提取的穿硅通孔（TSV）模型的方法和装置，其精确地对包括一个或多个TSV的插入器衬底进行建模。 在一些实施例中，通过产生具有对TSV进行建模的子电路的插入器晶片模型来执行方法。 子电路可以补偿由EDA工具执行的传统TSV模型的电阻和电容提取的限制。 在一些实施例中，子电路耦合到模型的浮动公共节点。 浮动公共节点使得插入器晶片模型能够考虑插入器内的电容耦合。 改进的插入器晶片模型能够使具有一个或多个TSV的插入件的精确RC提取，从而提供在GDS和APR流之间一致的插入器晶片模型。

公开(公告)号：US09003345B2

公开(公告)日：2015-04-07

申请号：US13925870

申请日：2013-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Fan Wu ,  Ke-Ying Su ,  Hsien-Hsin Sean Lee

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5072

Abstract: A method generally comprises arranging a plurality of layer combinations into a plurality of groups such that each of the layer combinations is assigned to at least one group. A shifting analysis is performed on a plurality of benchmark circuits for each of the groups. At least one tuning vector value is calculated based, at least in part, on a plurality of criteria vectors of the benchmark circuits. A shift is applied on each of the groups by the tuning vector value and a technology file, such as a 2.5 dimensional RC techfile, is regenerated.

Abstract translation: 方法通常包括将多个层组合布置成多个组，使得每个层组合被分配给至少一个组。 对于每个组的多个基准电路执行移位分析。 至少部分地基于基准电路的多个标准向量来计算至少一个调谐向量值。 通过调谐向量值对每个组应用偏移，并且再生出诸如2.5维RC技术文件的技术文件。

公开(公告)号：US08954900B1

公开(公告)日：2015-02-10

申请号：US13955313

申请日：2013-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ming Ho ,  Kun-Ting Tsai ,  Tsung-Han Wu ,  Ke-Ying Su ,  Hsien-Hsin Sean Lee

IPC: G06F17/50

CPC classification number: G03F7/70466 ,  G03F7/70433

Abstract: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. The patterns are divided into first and second groups, to be patterned on the single layer by a first mask or a second mask. For each portion of each pattern, a spacing relationship is determined between that portion and any adjacent pattern on either or both sides. A processor computes a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second cost of assigning the first group to the second mask and the second group to the first mask, based on the spacing relationships. The first group is assigned to the first mask and the second group to the second mask if the first cost is lower than the second cost.

Abstract translation: 集成电路的单层布局的一部分是多图案化的。 图案被划分为第一和第二组，通过第一掩模或第二掩模在单层上图案化。 对于每个图案的每个部分，在该部分和任一侧或两侧上的任何相邻图案之间确定间隔关系。 处理器计算将第一组分配给第一屏蔽，将第二组分配给第二屏蔽的第一电容（C），电阻（R）或电阻 - 电容（RC）成本，以及分配第一组的第二成本 基于间隔关系将第二掩模和第二组移动到第一掩模。 如果第一个成本低于第二个成本，则第一组被分配给第一个掩码，第二个组分配给第二个掩码。

公开(公告)号：US08887116B2

公开(公告)日：2014-11-11

申请号：US13906614

申请日：2013-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ming Ho ,  Te-Yu Liu ,  Austin Chingyu Chiang ,  Meng-Fan Wu ,  Ke-Ying Su

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: The present disclosure relates to a method of RC extraction that provides for a fast development time and easy maintenance. In some embodiments, the method provides a graphical representation of an integrated chip layout having a plurality of integrated chip components. A plurality of pattern based graphical features are then determined. Respective pattern based graphical features define a structural aspect of an integrated chip component. One of the plurality of integrated chip components is defined as a pattern oriented function having inputs of one or more of the pattern based graphical features. The pattern oriented function determines a shape of the one of the plurality of integrated chip components based upon a relation between the plurality of inputs. By determining a shape of an integrated chip component using a pattern oriented function, the complexity of RC profiles can be reduced.

Abstract translation: 本公开涉及一种提供快速开发时间和易于维护的RC提取方法。 在一些实施例中，该方法提供具有多个集成芯片组件的集成芯片布局的图形表示。 然后确定多个基于图案的图形特征。 基于图案的图形特征定义了集成芯片组件的结构方面。 多个集成芯片组件中的一个被定义为具有基于图案的图形特征中的一个或多个的输入的具有图案的功能。 基于图案的功能基于多个输入之间的关系确定多个集成芯片组件中的一个的形状。 通过使用面向图案的功能确定集成芯片组件的形状，可以减小RC轮廓的复杂性。