公开(公告)号：US20190252547A1

公开(公告)日：2019-08-15

申请号：US16396852

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Barn CHEN ,  Ting-Huang KUO ,  Shiu-Ko JANGJIAN ,  Chi-Cherng JENG

IPC: H01L29/78 ,  H01L49/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L29/7851 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/66795

Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure over a substrate, and a second fin structure over the substrate. The FinFET device structure also includes a first isolation structure over the substrate and surrounding the first fin structure. The first fin structure is protruded from a top surface of the first isolation structure. The FinFET device structure further includes a second isolation structure over the substrate and surrounding the second fin structure. The second fin structure is protruded from a top surface of the second isolation structure, and the first fin structure has a vertical sidewall surface and the second fin structure has a sloped sidewall surface.

公开(公告)号：US20220262680A1

公开(公告)日：2022-08-18

申请号：US17740241

申请日：2022-05-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Barn CHEN ,  Ting-Huang KUO ,  Shiu-Ko JANGJIAN ,  Chi-Cherng JENG ,  Kuang-Yao LO

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/308 ,  H01L21/265 ,  H01L27/088 ,  H01L29/08

Abstract: A device includes a FinFET on a first region of a substrate and a planar-FET on a second region of the substrate. The FinFET includes a FinFET source region, a FinFET drain region, and a FinFET gate between the FinFET source region and the FinFET drain region. The planar-FET includes a planar-FET source region, a planar-FET drain region, and a planar-FET gate between the planar-FET source region and the planar-FET drain region. A bottommost position of the FinFET source region is lower than a bottommost position of the planar-FET source region.

公开(公告)号：US20200051978A1

公开(公告)日：2020-02-13

申请号：US16657528

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Barn CHEN ,  Chi-Cherng JENG ,  Shiu-Ko JANGJIAN ,  Ting-Huang KUO

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06

Abstract: The present disclosure describes an exemplary asymmetric CPP layout for a semiconductor structure with a different gate pitch over the source and the drain regions to mitigate gate-to-gate parasitic capacitances over the drain region, thus improving cutoff frequency. For example, the semiconductor structure can include a fin on a substrate. The semiconductor structure can also include first and second gate structures formed on the fin and separated by a first space. The semiconductor structure can also include a third gate structure formed on the fin between the first and the second gate structures. The third gate structure can be separated from the first gate structure by a second pitch and separated from the second gate structure by a third pitch that is greater than the second pitch. The semiconductor structure further includes a source region formed between the first and third gate structures, and a drain region formed between the third and the second gate structures.

公开(公告)号：US20200091004A1

公开(公告)日：2020-03-19

申请号：US16687605

申请日：2019-11-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Barn CHEN ,  Ting-Huang KUO ,  Shiu-Ko JANGJIAN ,  Chi-Cherng JENG ,  Kuang-Yao LO

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/308 ,  H01L29/66 ,  H01L29/08 ,  H01L27/088

Abstract: A device includes first and second transistors and first and second isolation structures. The first transistor includes an active region including a first channel region, a first source and a first drain in the active region and respectively on opposite sides of the first channel region, and a first gate structure over the first channel region. The first isolation structure surrounds the active region of the first transistor. The second transistor includes a second source and a second drain, a fin structure includes a second channel region between the second source and the second drain, and a second gate structure over the second channel region. The second isolation structure surrounds a bottom portion of the fin structure of the second transistor. The top of the first isolation structure is higher than a top of the second isolation structure.

公开(公告)号：US20240297079A1

公开(公告)日：2024-09-05

申请号：US18662772

申请日：2024-05-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Barn CHEN ,  Ting-Huang KUO ,  Shiu-Ko JANGJIAN ,  Chi-Cherng JENG ,  Kuang-Yao LO

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/308 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L21/823412 ,  H01L21/26513 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66545 ,  H01L21/823418 ,  H01L21/823468

Abstract: A device includes a FinFET on a first region of a substrate and a planar-FET on a second region of the substrate. The FinFET includes a FinFET source region, a FinFET drain region, and a FinFET gate between the FinFET source region and the FinFET drain region. The planar-FET includes a planar-FET source region, a planar-FET drain region, and a planar-FET gate between the planar-FET source region and the planar-FET drain region. A bottommost position of the FinFET source region is lower than a bottommost position of the planar-FET source region.

公开(公告)号：US20210043517A1

公开(公告)日：2021-02-11

申请号：US17079052

申请日：2020-10-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Barn CHEN ,  Ting-Huang KUO ,  Shiu-Ko JANGJIAN ,  Chi-Cherng JENG ,  Kuang-Yao LO

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/308 ,  H01L21/265 ,  H01L27/088 ,  H01L29/08

Abstract: A device includes first and second transistors and first and second isolation structures. The first transistor includes a raised structure, a first gate structure over the raised structure, and a first source/drain structure over the raised structure and adjacent the first gate structure. The first isolation structure surrounds the raised structure and the first source/drain structure of the first transistor. A bottommost surface of the first source/drain structure is spaced apart from a topmost surface of the first isolation structure. The second transistor includes a fin structure, a second gate structure over the raised structure, and a second source/drain structure over the fin structure. The second isolation structure surrounds a bottom of the fin structure of the second transistor. A bottommost surface of the second source/drain structure is in contact with a topmost surface of the second isolation structure.

公开(公告)号：US20190067483A1

公开(公告)日：2019-02-28

申请号：US15692085

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Barn CHEN ,  Ting-Huang KUO ,  Shiu-Ko JANGJIAN ,  Chi-Cherng JENG

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/66 ,  H01L27/06

Abstract: A FinFET device structure and method for forming the same are provided. The method includes forming a plurality of fin structures over a substrate, and the substrate includes a first region and a second region. The method includes forming a plurality of isolation structures surrounding the fin structures, and a top surface of each of the isolation structures is lower than a top surface of each of the fin structures, and the isolation structures include first isolation structures over the first region and second isolation structures over the second region. The method includes forming a mask layer on the first isolation structures to expose the second isolation structures and removing a portion of the second isolation structures, such that a top surface of each of the second isolation structures is lower than a top surface of each of the first isolation structures.

公开(公告)号：US20190057905A1

公开(公告)日：2019-02-21

申请号：US15678097

申请日：2017-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Barn CHEN ,  Ting-Huang KUO ,  Shiu-Ko JANGJIAN ,  Chi-Cherng JENG ,  Kuang-Yao LO

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/308 ,  H01L21/265

Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. A hard mask and a mask layer are formed on a first region and a second region of the substrate. The substrate is recessed using the hard mask and the mask layer to form a fin structure in the first region and a raised structure in the second region. First isolation structures and second isolation structures are formed on lower portions of opposite sidewalls of the fin structure and opposite sidewalls of the raised structure. A first gate structure is formed on a portion of the fin structure, and a second gate structure is formed on a portion of the raised structure. A first source and a first drain are formed on opposite sides of the first gate structure, and a second source and a second drain are formed on opposite sides of the second gate structure.