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    SEMICONDUCTOR DEVICE HAVING PLANAR TRANSISTOR AND FINFET
    1.
    发明申请
    SEMICONDUCTOR DEVICE HAVING PLANAR TRANSISTOR AND FINFET 审中-公开

    公开(公告)号：US20200091004A1

    公开(公告)日：2020-03-19

    申请号：US16687605

    申请日：2019-11-18

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Barn CHEN ,  Ting-Huang KUO ,  Shiu-Ko JANGJIAN ,  Chi-Cherng JENG ,  Kuang-Yao LO

    IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/308 ,  H01L29/66 ,  H01L29/08 ,  H01L27/088

    Abstract: A device includes first and second transistors and first and second isolation structures. The first transistor includes an active region including a first channel region, a first source and a first drain in the active region and respectively on opposite sides of the first channel region, and a first gate structure over the first channel region. The first isolation structure surrounds the active region of the first transistor. The second transistor includes a second source and a second drain, a fin structure includes a second channel region between the second source and the second drain, and a second gate structure over the second channel region. The second isolation structure surrounds a bottom portion of the fin structure of the second transistor. The top of the first isolation structure is higher than a top of the second isolation structure.

    SEMICONDUCTOR DEVICE HAVING PLANAR TRANSISTOR AND FINFET
    7.
    发明申请
    SEMICONDUCTOR DEVICE HAVING PLANAR TRANSISTOR AND FINFET 有权

    公开(公告)号：US20210043517A1

    公开(公告)日：2021-02-11

    申请号：US17079052

    申请日：2020-10-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Barn CHEN ,  Ting-Huang KUO ,  Shiu-Ko JANGJIAN ,  Chi-Cherng JENG ,  Kuang-Yao LO

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/308 ,  H01L21/265 ,  H01L27/088 ,  H01L29/08

    Abstract: A device includes first and second transistors and first and second isolation structures. The first transistor includes a raised structure, a first gate structure over the raised structure, and a first source/drain structure over the raised structure and adjacent the first gate structure. The first isolation structure surrounds the raised structure and the first source/drain structure of the first transistor. A bottommost surface of the first source/drain structure is spaced apart from a topmost surface of the first isolation structure. The second transistor includes a fin structure, a second gate structure over the raised structure, and a second source/drain structure over the fin structure. The second isolation structure surrounds a bottom of the fin structure of the second transistor. A bottommost surface of the second source/drain structure is in contact with a topmost surface of the second isolation structure.

    FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
    8.
    发明申请
    FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开

    公开(公告)号：US20190067483A1

    公开(公告)日：2019-02-28

    申请号：US15692085

    申请日：2017-08-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Barn CHEN ,  Ting-Huang KUO ,  Shiu-Ko JANGJIAN ,  Chi-Cherng JENG

    IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/66 ,  H01L27/06

    Abstract: A FinFET device structure and method for forming the same are provided. The method includes forming a plurality of fin structures over a substrate, and the substrate includes a first region and a second region. The method includes forming a plurality of isolation structures surrounding the fin structures, and a top surface of each of the isolation structures is lower than a top surface of each of the fin structures, and the isolation structures include first isolation structures over the first region and second isolation structures over the second region. The method includes forming a mask layer on the first isolation structures to expose the second isolation structures and removing a portion of the second isolation structures, such that a top surface of each of the second isolation structures is lower than a top surface of each of the first isolation structures.

    METHOD FOR MANUFACTURING DUAL FINFET DEVICE
    9.
    发明申请
    METHOD FOR MANUFACTURING DUAL FINFET DEVICE 审中-公开

    公开(公告)号：US20190057905A1

    公开(公告)日：2019-02-21

    申请号：US15678097

    申请日：2017-08-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Barn CHEN ,  Ting-Huang KUO ,  Shiu-Ko JANGJIAN ,  Chi-Cherng JENG ,  Kuang-Yao LO

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/308 ,  H01L21/265

    Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. A hard mask and a mask layer are formed on a first region and a second region of the substrate. The substrate is recessed using the hard mask and the mask layer to form a fin structure in the first region and a raised structure in the second region. First isolation structures and second isolation structures are formed on lower portions of opposite sidewalls of the fin structure and opposite sidewalls of the raised structure. A first gate structure is formed on a portion of the fin structure, and a second gate structure is formed on a portion of the raised structure. A first source and a first drain are formed on opposite sides of the first gate structure, and a second source and a second drain are formed on opposite sides of the second gate structure.

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