公开(公告)号：US20210043443A1

公开(公告)日：2021-02-11

申请号：US16534310

申请日：2019-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-He Chou ,  Sheng-Chau Chen ,  Ming-Tung Wu ,  Hsun-Chung Kuang

IPC: H01L21/02 ,  B08B5/02 ,  B08B3/10 ,  H01L21/67 ,  H01L21/687

Abstract: In some embodiments, the present disclosure relates to a wafer trimming and cleaning apparatus, which includes a blade that is configured to trim a damaged edge portion of a wafer, thereby defining a new sidewall of the wafer. The wafer trimming and cleaning apparatus further includes water nozzles and an air jet nozzle. The water nozzles are configured to apply deionized water to the new sidewall of the wafer to remove contaminant particles generated by the blade. The air jet nozzle is configured to apply pressurized gas to a first top surface area of the wafer to remove the contaminant particles generated by the blade. The first top surface area overlies the new sidewall of the wafer.

公开(公告)号：US11445104B2

公开(公告)日：2022-09-13

申请号：US16822424

申请日：2020-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Shu Huang ,  Ming Chyi Liu ,  Tung-He Chou

IPC: H01L29/00 ,  H04N5/232 ,  G03B13/36 ,  H04N5/247 ,  G01S3/00 ,  H01L21/00 ,  G06V10/40 ,  G06V10/75 ,  G06V40/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/3213 ,  H04N5/225 ,  H04N5/262

Abstract: Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.

公开(公告)号：US20210193453A1

公开(公告)日：2021-06-24

申请号：US17088805

申请日：2020-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tung Wu ,  Hsun-Chung Kuang ,  Tung-He Chou

IPC: H01L21/02 ,  B23K26/53 ,  B23K26/03 ,  H01L21/268 ,  H01L21/304 ,  H01L23/544 ,  H01L21/66

Abstract: In some embodiments, the present disclosure relates to a method that includes aligning a stealth laser apparatus over a wafer using an infrared camera coupled to the stealth laser apparatus. The stealth laser apparatus is used to form a stealth damage region within the wafer that is continuously connected around the wafer and separates an inner region from an outer region of the wafer. The stealth damage region is also arranged at a first distance from an edge of the wafer and extends from a first depth to a second depth beneath a top surface of the wafer. Further, the method includes forming a groove in the wafer to separate the outer region from the inner region of the wafer. The outer region of the wafer is removed using a blade, and a top portion of the inner region of the wafer is removed using a grinding apparatus.

公开(公告)号：US11901171B2

公开(公告)日：2024-02-13

申请号：US17088805

申请日：2020-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tung Wu ,  Hsun-Chung Kuang ,  Tung-He Chou

IPC: H01L21/02 ,  B23K26/53 ,  B23K26/03 ,  H01L21/268 ,  H01L23/544 ,  H01L21/66 ,  H01L21/304 ,  B23K103/00

CPC classification number: H01L21/02021 ,  B23K26/032 ,  B23K26/53 ,  H01L21/268 ,  H01L21/3043 ,  H01L22/20 ,  H01L23/544 ,  B23K2103/56 ,  H01L2223/54426 ,  H01L2223/54493

Abstract: In some embodiments, the present disclosure relates to a method that includes aligning a stealth laser apparatus over a wafer using an infrared camera coupled to the stealth laser apparatus. The stealth laser apparatus is used to form a stealth damage region within the wafer that is continuously connected around the wafer and separates an inner region from an outer region of the wafer. The stealth damage region is also arranged at a first distance from an edge of the wafer and extends from a first depth to a second depth beneath a top surface of the wafer. Further, the method includes forming a groove in the wafer to separate the outer region from the inner region of the wafer. The outer region of the wafer is removed using a blade, and a top portion of the inner region of the wafer is removed using a grinding apparatus.

公开(公告)号：US11081334B2

公开(公告)日：2021-08-03

申请号：US16534310

申请日：2019-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-He Chou ,  Sheng-Chau Chen ,  Ming-Tung Wu ,  Hsun-Chung Kuang

IPC: H01L21/02 ,  B08B5/02 ,  H01L21/687 ,  H01L21/67 ,  B08B3/10

Abstract: In some embodiments, the present disclosure relates to a wafer trimming and cleaning apparatus, which includes a blade that is configured to trim a damaged edge portion of a wafer, thereby defining a new sidewall of the wafer. The wafer trimming and cleaning apparatus further includes water nozzles and an air jet nozzle. The water nozzles are configured to apply deionized water to the new sidewall of the wafer to remove contaminant particles generated by the blade. The air jet nozzle is configured to apply pressurized gas to a first top surface area of the wafer to remove the contaminant particles generated by the blade. The first top surface area overlies the new sidewall of the wafer.

公开(公告)号：US20200221015A1

公开(公告)日：2020-07-09

申请号：US16822424

申请日：2020-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Shu Huang ,  Ming Chyi Liu ,  Tung-He Chou

IPC: H04N5/232 ,  G03B13/36 ,  H04N5/247 ,  G01S3/00 ,  G06K9/00 ,  G06K9/46 ,  G06K9/62 ,  H04N5/225 ,  H04N5/262

Abstract: Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.