公开(公告)号：US11951569B2

公开(公告)日：2024-04-09

申请号：US17317977

申请日：2021-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Yung-Lung Lin ,  Hau-Yi Hsiao ,  Sheng-Chau Chen ,  Cheng-Yuan Tsai

IPC: H01L21/02 ,  B23K26/035 ,  B23K26/062 ,  B23K26/361 ,  H01L21/66

CPC classification number: B23K26/361 ,  B23K26/035 ,  B23K26/062 ,  H01L21/02021 ,  H01L22/10

Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.

公开(公告)号：US20230154898A1

公开(公告)日：2023-05-18

申请号：US18156848

申请日：2023-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Yung-Lung Lin ,  Zhi-Yang Wang ,  Sheng-Chau Chen ,  Cheng-Hsien Chou

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L24/06 ,  H01L24/02

Abstract: A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.

公开(公告)号：US20220157875A1

公开(公告)日：2022-05-19

申请号：US17097360

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Wei Liang ,  Sheng-Chau Chen ,  Hsun-Chung Kuang ,  Sheng-Chan Li

IPC: H01L27/146

Abstract: A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.

公开(公告)号：US11189583B2

公开(公告)日：2021-11-30

申请号：US16723041

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Shih-Pei Chou ,  Ming-Che Lee ,  Kuo-Ming Wu ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Yeur-Luen Tu

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/768

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.

公开(公告)号：US11081334B2

公开(公告)日：2021-08-03

申请号：US16534310

申请日：2019-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-He Chou ,  Sheng-Chau Chen ,  Ming-Tung Wu ,  Hsun-Chung Kuang

IPC: H01L21/02 ,  B08B5/02 ,  H01L21/687 ,  H01L21/67 ,  B08B3/10

Abstract: In some embodiments, the present disclosure relates to a wafer trimming and cleaning apparatus, which includes a blade that is configured to trim a damaged edge portion of a wafer, thereby defining a new sidewall of the wafer. The wafer trimming and cleaning apparatus further includes water nozzles and an air jet nozzle. The water nozzles are configured to apply deionized water to the new sidewall of the wafer to remove contaminant particles generated by the blade. The air jet nozzle is configured to apply pressurized gas to a first top surface area of the wafer to remove the contaminant particles generated by the blade. The first top surface area overlies the new sidewall of the wafer.

公开(公告)号：US20210210681A1

公开(公告)日：2021-07-08

申请号：US16733378

申请日：2020-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Tai Hsiao ,  Sheng-Chau Chen ,  Hsun-Chung Kuang

IPC: H01L45/00

Abstract: The problem of forming top electrode vias that provide consistent results in devices that include resistance switching RAM cells of varying heights is solved using a dielectric composite that fills areas between resistance switching RAM cells and varies in height to align with the tops of both the taller and the shorter resistance switching RAM cells. An etch stop layer may be formed over the dielectric composite providing an equal thickness of etch-resistant dielectric over both taller and shorter resistance switching RAM cells. The dielectric composite causes the etch stop layer to extend laterally away from the resistance switching RAM cells to maintain separation between the via openings and the resistance switching RAM cell sides even when the openings are misaligned.

公开(公告)号：US10964746B2

公开(公告)日：2021-03-30

申请号：US16405102

申请日：2019-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Shih Pei Chou ,  Chih-Yu Lai ,  Sheng-Chau Chen ,  Chih-Ta Chen ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC: H01L27/146 ,  H01L33/20 ,  H01L21/8238

Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.

公开(公告)号：US10529913B1

公开(公告)日：2020-01-07

申请号：US16051759

申请日：2018-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Cheng-Tai Hsiao ,  Cheng-Yuan Tsai ,  Hsun-Chung Kuang

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell disposed on a substrate, the MRAM cell comprises a magnetic tunnel junction (MTJ) disposed between a lower electrode and an upper electrode. A sidewall spacer arranged along opposite sidewalls of the MRAM cell. An upper interconnect wire directly contacting an upper surface of the upper electrode along an interface continuously extending from a first outer edge of the sidewall spacer to a second outer edge of the sidewall spacer.

公开(公告)号：US20200006638A1

公开(公告)日：2020-01-02

申请号：US16051759

申请日：2018-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Cheng-Tai Hsiao ,  Cheng-Yuan Tsai ,  Hsun-Chung Kuang

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell disposed on a substrate, the MRAM cell comprises a magnetic tunnel junction (MTJ) disposed between a lower electrode and an upper electrode. A sidewall spacer arranged along opposite sidewalls of the MRAM cell. An upper interconnect wire directly contacting an upper surface of the upper electrode along an interface continuously extending from a first outer edge of the sidewall spacer to a second outer edge of the sidewall spacer.

公开(公告)号：US20190221548A1

公开(公告)日：2019-07-18

申请号：US16367720

申请日：2019-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Sheng-Chau Chen ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yung-Lung Lin

IPC: H01L25/065 ,  H01L25/00 ,  H01L27/146 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49838 ,  H01L23/52 ,  H01L24/00 ,  H01L24/05 ,  H01L25/50 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: In some embodiments, the present disclosure relates to a method of forming a multi-dimensional integrated chip. The method includes forming a first plurality of interconnect layers within a first dielectric structure on a front-side of a first substrate and forming a second plurality of interconnect layers within a second dielectric structure on a front-side of a second substrate. A first redistribution layer coupled to the first plurality of interconnect layers is bonded to a second redistribution layer coupled to the second plurality of interconnect layers along an interface. A recess is formed within a back-side of the second substrate and over the second plurality of interconnect layers. A bond pad is formed within the recess. The bond pad is laterally separated from the first redistribution layer by a non-zero distance.