公开(公告)号：US20210240900A1

公开(公告)日：2021-08-05

申请号：US17023286

申请日：2020-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Wei PENG ,  Jiann-Tyng TZENG

IPC: G06F30/392 ,  H01L27/02 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528

Abstract: A method generating a layout diagram includes: arranging the layout diagram into rows; configuring one or more of the rows as combination rows, the combination-row-configuring including relative to a second direction substantially perpendicular to the first direction, setting a height of each of the one or more combination rows to be substantially equal to a sum of a first height of a first cell and a second height of a second cell, the first cell being different than the second cell, and the first height being different than the second height; and populating each of the one or more combination rows including: stacking a first instance of the first cell on a first instance of the second cell, or stacking a second instance of the second cell on a second instance of the first cell.

公开(公告)号：US20210082903A1

公开(公告)日：2021-03-18

申请号：US17092100

申请日：2020-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen YOUNG ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Jiann-Tyng TZENG ,  Shun-Li CHEN ,  Kam-Tou SIO ,  Shih-Wei PENG ,  Chun-Kuang CHEN ,  Ru-Gun LIU

IPC: H01L27/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  G06F30/394

Abstract: A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

公开(公告)号：US20180166431A1

公开(公告)日：2018-06-14

申请号：US15699990

申请日：2017-09-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Cheng LIN ,  Hui-Ting YANG ,  Shih-Wei PENG ,  Jiann-Tyng TZENG ,  Charles Chew-Yuen YOUNG ,  Chih-Ming LAI

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/088 ,  H01L27/0886

Abstract: A semiconductor device includes at least one first gate strip, at least one second gate strip, at least one first conductive line and at least one first conductive via. An end surface of the at least one first gate strip and an end surface of the at least one second gate strip are opposite each other. The at least one first conductive line is over the at least one first gate strip and the at least one second gate strip and across the end surface of the at least one first gate strip and the end surface of the at least one second gate strip. The at least one first conductive via connects the at least one first conductive line and the at least one first gate strip.

公开(公告)号：US20240362390A1

公开(公告)日：2024-10-31

申请号：US18768942

申请日：2024-07-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Wei PENG ,  Jiann-Tyng TZENG

IPC: G06F30/392 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092

CPC classification number: G06F30/392 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092

Abstract: A semiconductor device includes cell regions in rows, each row including at least one instance of a first or second cell region, each of the first and second cell regions including: structures in a transistor layer; conductive segments in an M_1st layer and extending substantially in a first direction (row direction), the M_1st layer having a first pitch as a sole pitch for the conductive segments of the M_1st layer; conductive segments in an M_2nd layer; and conductive segments in an M_3rd layer, including conductive segments for a power grid (PG segments) and conductive segments for control or data signals (logic segments), the M_3rd layer having a second pitch for the logic segments and a third pitch for the PG segments, the third pitch being greater than the second pitch, and the second pitch being different from the first pitch.

公开(公告)号：US20220352079A1

公开(公告)日：2022-11-03

申请号：US17868065

申请日：2022-07-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Wei PENG ,  Chia-Tien WU ,  Jiann-Tyng TZENG

IPC: H01L23/538 ,  H01L21/768

Abstract: An integrated circuit includes conductive rails that are disposed in a first conductive layer and separated from each other in a layout view, signal rails disposed in a second conductive layer different from the first conductive layer, at least one first via coupling a first signal rail of the signal rails to at least one of the conductive rails, and at least one first conductive segment. The first signal rail transmits a supply signal through the at least one first via and the at least one of the conductive rails to at least one element of the integrated circuit. The at least one first via and the at least one first conductive segment are disposed above first conductive layer. The at least one first conductive segment is coupled to the at least one of the conductive rails and is separate from the first signal rail.

公开(公告)号：US20210098453A1

公开(公告)日：2021-04-01

申请号：US17120839

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei PENG ,  Hui-Zhong ZHUANG ,  Jiann-Tyng TZENG ,  Li-Chun TIEN ,  Pin-Dai SUE ,  Wei-Cheng LIN

IPC: H01L27/092 ,  H03K17/687

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

公开(公告)号：US20210064806A1

公开(公告)日：2021-03-04

申请号：US16850849

申请日：2020-04-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Wei PENG ,  Chih-Ming LAI ,  Jiann-Tyng TZENG

IPC: G06F30/392 ,  H01L23/538

Abstract: A method of generating an integrated circuit (IC) layout diagram includes arranging first conductive feature layout patterns in a cell region. The first conductive feature layout patterns extend in a first direction, and the cell region has opposite first and second cell boundaries extending in a second direction. Second conductive feature layout patterns are arranged in the cell region and extending in the first direction. The first and second conductive feature layout patterns are alternately arranged. First cut feature layout patterns are arranged on the first cell boundary of the cell region and on ends of the first conductive feature layout patterns. One of the first cut feature layout patterns is offset from another one of the first cut feature layout patterns in the first direction. The IC layout diagram including the first and second conductive feature layout patterns and the first cut feature layout patterns is generated.

公开(公告)号：US20240178139A1

公开(公告)日：2024-05-30

申请号：US18437130

申请日：2024-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-An LAI ,  Shih-Wei PENG ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L23/528 ,  G06F30/31 ,  G06F30/394 ,  G06F30/398 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L23/528 ,  G06F30/394 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696 ,  G06F30/31 ,  G06F30/398

Abstract: Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.

公开(公告)号：US20220359512A1

公开(公告)日：2022-11-10

申请号：US17875060

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei PENG ,  Hui-Zhong ZHUANG ,  Jiann-Tyng TZENG ,  Li-Chun TIEN ,  Pin-Dai SUE ,  Wei-Cheng LIN

IPC: H01L27/092 ,  H03K17/687

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

公开(公告)号：US20240379554A1

公开(公告)日：2024-11-14

申请号：US18784733

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei PENG ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/522

Abstract: Apparatus and methods for back side routing a data signal in a semiconductor device are described. In one example, a described semiconductor cell structure includes: a dummy device region at a front side of the semiconductor cell structure; a metal layer including a plurality of metal lines at a back side of the semiconductor cell structure; a dielectric layer formed between the dummy device region and the metal layer; an inner metal disposed within the dielectric layer; at least one first via that is formed through the dielectric layer and electrically connects the inner metal to the plurality of metal lines at the back side; and at least one second via that is formed in the dielectric layer and physically coupled between the inner metal and the dummy device region at the front side.