公开(公告)号：US11062739B2

公开(公告)日：2021-07-13

申请号：US16454076

申请日：2019-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Wei-Chang Zhao

IPC: H01L27/11 ,  H01L27/092 ,  G11C5/06

Abstract: A semiconductor chip is provided. The semiconductor chip includes a memory cell and a logic cell disposed aside the memory cell, and includes signal and ground lines with the memory and logic cells located therebetween. The memory cell includes first and second active structures extending along a first direction, and includes a storage transmission gate line, first through third gate lines and a read transmission gate line extending along a second direction. The storage transmission gate line includes first and second line segments, which respectively extends across the active structures. The first through third gate lines continuously extend across the first and second active structures. The read transmission gate line includes third and fourth line segments, which respectively extend across the active structures. The first through third gate lines are located between the storage and read transmission gate lines.

公开(公告)号：US12230318B2

公开(公告)日：2025-02-18

申请号：US17871635

申请日：2022-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Hsin Nien ,  Wei-Chang Zhao ,  Chih-Yu Lin ,  Hidehiro Fujiwara ,  Yen-Huei Chen ,  Ru-Yu Wang

IPC: G11C11/419 ,  G11C5/06 ,  G11C11/412

Abstract: A memory device includes a first word line and a second word line. A first portion of the first word line is formed in a first metal layer, a second portion of the first word line is formed in a second metal layer above the first metal layer, and a third portion of the first word line is formed in a third metal layer below the second metal layer. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. The first portion, the second portion, and the third portion of the first word line have sizes that are different from each other, and the first portion and the second portion of the second word line have sizes that are different from each other.

公开(公告)号：US11805636B2

公开(公告)日：2023-10-31

申请号：US17035148

申请日：2020-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Hsin Nien ,  Chih-Yu Lin ,  Wei-Chang Zhao ,  Hidehiro Fujiwara

IPC: H10B10/00 ,  H01L23/522 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/528

CPC classification number: H10B10/12 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283

Abstract: A memory device is disclosed. The memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer, and a second portion of the second program line is formed in a third conductive layer above the second conductive layer. A width of at least one of the second portion of the first program line or the second portion of the second program line is different from a width of at least one of the first portion of the first program line or the first portion of the second program line. A method is also disclosed herein.