公开(公告)号：US20230385521A1

公开(公告)日：2023-11-30

申请号：US18447455

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin CHUANG ,  Shih-Yao LIN ,  Szu-ju HUANG ,  Yin-An CHEN ,  Shih Feng HONG

IPC: G06F30/398 ,  G06N20/00 ,  G06F30/392 ,  G06F30/394 ,  G06F30/327

CPC classification number: G06F30/398 ,  G06N20/00 ,  G06F30/327 ,  G06F30/394 ,  G06F30/392

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

公开(公告)号：US20240394460A1

公开(公告)日：2024-11-28

申请号：US18790306

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin CHUANG ,  Shih-Yao LIN ,  Szu-ju HUANG ,  Yin-An CHEN ,  Shih Feng HONG

IPC: G06F30/398 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06N20/00

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

公开(公告)号：US20230385520A1

公开(公告)日：2023-11-30

申请号：US18446745

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin CHUANG ,  Shih-Yao LIN ,  Szu-ju HUANG ,  Yin-An CHEN ,  Shih Feng HONG

IPC: G06F30/398 ,  G06N20/00 ,  G06F30/392 ,  G06F30/394 ,  G06F30/327

CPC classification number: G06F30/398 ,  G06N20/00 ,  G06F30/392 ,  G06F30/394 ,  G06F30/327

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.