公开(公告)号：US20240394460A1

公开(公告)日：2024-11-28

申请号：US18790306

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin CHUANG ,  Shih-Yao LIN ,  Szu-ju HUANG ,  Yin-An CHEN ,  Shih Feng HONG

IPC: G06F30/398 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06N20/00

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

公开(公告)号：US20240104285A1

公开(公告)日：2024-03-28

申请号：US18526337

申请日：2023-12-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC NANJING COMPANY LIMITED

Inventor： Yi-Lin CHUANG ,  Shi-Wen TAN ,  Song LIU ,  Shih-Yao LIN ,  Wen-Yuan FANG

IPC: G06F30/392 ,  G06F30/373 ,  G06F30/394 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/373 ,  G06F30/394 ,  G06F30/398

Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.

公开(公告)号：US20230385520A1

公开(公告)日：2023-11-30

申请号：US18446745

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin CHUANG ,  Shih-Yao LIN ,  Szu-ju HUANG ,  Yin-An CHEN ,  Shih Feng HONG

IPC: G06F30/398 ,  G06N20/00 ,  G06F30/392 ,  G06F30/394 ,  G06F30/327

CPC classification number: G06F30/398 ,  G06N20/00 ,  G06F30/392 ,  G06F30/394 ,  G06F30/327

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

公开(公告)号：US20230385521A1

公开(公告)日：2023-11-30

申请号：US18447455

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin CHUANG ,  Shih-Yao LIN ,  Szu-ju HUANG ,  Yin-An CHEN ,  Shih Feng HONG

IPC: G06F30/398 ,  G06N20/00 ,  G06F30/392 ,  G06F30/394 ,  G06F30/327

CPC classification number: G06F30/398 ,  G06N20/00 ,  G06F30/327 ,  G06F30/394 ,  G06F30/392

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

公开(公告)号：US20220382950A1

公开(公告)日：2022-12-01

申请号：US17883246

申请日：2022-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC NANJING COMPANY LIMITED

Inventor： Yi-Lin CHUANG ,  Shi-Wen TAN ,  Song LIU ,  Shih-Yao LIN ,  Wen-Yuan FANG

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/373 ,  G06F30/398

Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.

公开(公告)号：US20220092248A1

公开(公告)日：2022-03-24

申请号：US17071862

申请日：2020-10-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC NANJING COMPANY LIMITED

Inventor： Yi-Lin CHUANG ,  Shi-Wen TAN ,  Song LIU ,  Shih-Yao LIN ,  Wen-Yuan FANG

IPC: G06F30/392

Abstract: A method is provided in the present disclosure. The method includes several operations: generating a floor plan having multiple macros for an integrated circuit; adjusting the macros according to a channel area interposed between the pins; separating the macros by a channel width of the channel area; and adjusting, in accordance with correlations between the macros and multiple registers, the macros in the floor plan.

公开(公告)号：US20220366118A1

公开(公告)日：2022-11-17

申请号：US17875139

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC NANJING COMPANY LIMITED

Inventor： Yi-Lin CHUANG ,  Shi-Wen TAN ,  Song LIU ,  Shih-Yao LIN ,  Wen-Yuan FANG

IPC: G06F30/392 ,  G06F30/373 ,  G06F30/398 ,  G06F30/394

Abstract: A method is provided and includes several operations: forming a first group of macros in a first region, wherein the first group of macros are aligned with a first boundary of a channel that is coupled thereto through pins of the first group of macros; forming a second group of macros in the first region to align with a second boundary of the channel that is coupled thereto through pins of the second group of macros, wherein the first and second groups of macros are coupled to a first register; and forming a third group of macros in a second region different from the first region. A first macro and a second macro that are in the third group of macros are aligned with the first and second boundaries respectively. The third group of macros are coupled to a second register different from the first register.

公开(公告)号：US20250107207A1

公开(公告)日：2025-03-27

申请号：US18974319

申请日：2024-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng LAI ,  Wei-Chung SUN ,  Yu-Bey WU ,  Yuan-Ching PENG ,  Yu-Shan LU ,  Li-Ting CHEN ,  Shih-Yao LIN ,  Yu-Fan PENG ,  Kuei-Yu KAO ,  Chih-Han LIN ,  Jing Yi YAN ,  Pei-Yi LIU

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.