公开(公告)号：US20210098636A1

公开(公告)日：2021-04-01

申请号：US16747503

申请日：2020-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chih-Hao Chang ,  Chia-Hung Liu ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Po-Chun Lin

IPC: H01L31/0203 ,  H01L31/18 ,  H01L31/024 ,  H01L31/02

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure. A method of forming the semiconductor package is also provided.

公开(公告)号：US11527525B2

公开(公告)日：2022-12-13

申请号：US17113204

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Cheng Tseng ,  Yu-Chih Huang ,  Chih-Hsuan Tai ,  Ting-Ting Kuo ,  Chi-Hui Lai ,  Ban-Li Wu ,  Chiahung Liu ,  Hao-Yi Tsai

IPC: H01L27/01 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L21/768 ,  H01L21/70 ,  H01L23/522 ,  H01L25/10

Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

公开(公告)号：US20210091065A1

公开(公告)日：2021-03-25

申请号：US17113204

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Cheng Tseng ,  Yu-Chih Huang ,  Chih-Hsuan Tai ,  Ting-Ting Kuo ,  Chi-Hui Lai ,  Ban-Li Wu ,  Chiahung Liu ,  Hao-Yi Tsai

IPC: H01L27/01 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L21/768 ,  H01L21/70 ,  H01L23/522

Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

公开(公告)号：US20200294912A1

公开(公告)日：2020-09-17

申请号：US16354173

申请日：2019-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Tsung-Hsien Chiang ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Po-Chun Lin

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

Abstract: A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.

公开(公告)号：US20200058626A1

公开(公告)日：2020-02-20

申请号：US16103921

申请日：2018-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Chi-Hui Lai

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

公开(公告)号：US20210242159A1

公开(公告)日：2021-08-05

申请号：US16897296

申请日：2020-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Sen-Kuei Hsu ,  Tin-Hao Kuo ,  Yi-Yang Lei ,  Ying-Cheng Tseng ,  Chi-Hui Lai

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L21/48 ,  H01L21/683

Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.

公开(公告)号：US11011501B2

公开(公告)日：2021-05-18

申请号：US16103921

申请日：2018-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Chi-Hui Lai

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

公开(公告)号：US20210074694A1

公开(公告)日：2021-03-11

申请号：US17099179

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chih Huang ,  Chi-Hui Lai ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Ting-Ting Kuo ,  Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Chuei-Tang Wang ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Chiahung Liu

IPC: H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

公开(公告)号：US10074615B1

公开(公告)日：2018-09-11

申请号：US15794003

申请日：2017-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Cheng Tseng ,  Chih-Hua Chen ,  Hsiu-Jen Lin ,  Hao-Yi Tsai ,  Kuo-Chung Yee ,  Chia-Hung Liu

IPC: H01L23/552 ,  H01L23/34 ,  H01L23/538 ,  H01L21/02

Abstract: A package structure including at least one conductive plate, a redistribution layer, a first semiconductor chip, a conductive shielding structure and an insulating encapsulant is provided. The first semiconductor chip is sandwiched in between the at least one conductive plate and the redistribution layer, wherein the first semiconductor chip is disposed on the at least one conductive plate and electrically connected to the redistribution layer. The conductive shielding structure is sandwiched in between the at least one conductive plate and the redistribution layer, wherein the conductive shielding structure surrounds the first semiconductor chip and electrically connects the at least one conductive plate with the redistribution layer. The insulating encapsulant is disposed on the redistribution layer, encapsulating the first semiconductor chip, the conductive shielding structure, and surrounding the at least one conductive plate.

公开(公告)号：US11374136B2

公开(公告)日：2022-06-28

申请号：US16747503

申请日：2020-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chih-Hao Chang ,  Chia-Hung Liu ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Po-Chun Lin

IPC: H01L31/0203 ,  H01L31/18 ,  H01L31/024 ,  H01L31/02

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure. A method of forming the semiconductor package is also provided.