公开(公告)号：US10762319B2

公开(公告)日：2020-09-01

申请号：US15884287

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Tai ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo ,  Ying-Cheng Tseng

IPC: G06K9/00 ,  H01L21/70

Abstract: A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.

公开(公告)号：US20190236326A1

公开(公告)日：2019-08-01

申请号：US15884287

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Tai ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo ,  Ying-Cheng Tseng

IPC: G06K9/00 ,  H01L21/70

Abstract: A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.

公开(公告)号：US11011501B2

公开(公告)日：2021-05-18

申请号：US16103921

申请日：2018-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Chi-Hui Lai

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

公开(公告)号：US20210074694A1

公开(公告)日：2021-03-11

申请号：US17099179

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chih Huang ,  Chi-Hui Lai ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Ting-Ting Kuo ,  Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Chuei-Tang Wang ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Chiahung Liu

IPC: H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

公开(公告)号：US11842993B2

公开(公告)日：2023-12-12

申请号：US18064690

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Cheng Tseng ,  Yu-Chih Huang ,  Chih-Hsuan Tai ,  Ting-Ting Kuo ,  Chi-Hui Lai ,  Ban-Li Wu ,  Chiahung Liu ,  Hao-Yi Tsai

IPC: H01L27/01 ,  H01L21/70 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L25/10

CPC classification number: H01L27/013 ,  H01L21/705 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L24/13 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

公开(公告)号：US20230290747A1

公开(公告)日：2023-09-14

申请号：US17826519

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hung Chen ,  Cheng-Pu Chiu ,  Chien-Chen Li ,  Chien-Li Kuo ,  Ting-Ting Kuo ,  Li-Hsien Huang ,  Yao-Chun Chuang ,  Jun He

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L24/06 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2224/06519 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: Embodiments provide metal features which dissipate heat generated from a laser drilling process for exposing dummy pads through a dielectric layer. Because the dummy pads are coupled to the metal features, the metal features act as a heat dissipation feature to pull heat from the dummy pad. As a result, reduction in heat is achieved at the dummy pad during the laser drilling process.

公开(公告)号：US20230253384A1

公开(公告)日：2023-08-10

申请号：US18301555

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chih Huang ,  Chi-Hui Lai ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Ting-Ting Kuo ,  Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Chuei-Tang Wang ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Chiahung Liu

IPC: H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L25/162 ,  H01L21/50 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/20 ,  H01L25/16 ,  H01L25/105 ,  H01G4/00 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08225 ,  H01L2224/16235 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/15313 ,  H01L2924/19011 ,  H01L2924/19105

Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

公开(公告)号：US11631658B2

公开(公告)日：2023-04-18

申请号：US17099179

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chih Huang ,  Chi-Hui Lai ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Ting-Ting Kuo ,  Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Chuei-Tang Wang ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Chiahung Liu

IPC: H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01G4/00 ,  H01L25/065

Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

公开(公告)号：US20230110420A1

公开(公告)日：2023-04-13

申请号：US18064690

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Cheng Tseng ,  Yu-Chih Huang ,  Chih-Hsuan Tai ,  Ting-Ting Kuo ,  Chi-Hui Lai ,  Ban-Li Wu ,  Chiahung Liu ,  Hao-Yi Tsai

IPC: H01L27/01 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768 ,  H01L21/70 ,  H01L23/522

Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

公开(公告)号：US11309225B2

公开(公告)日：2022-04-19

申请号：US16714801

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Tai ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo

IPC: H01L23/31 ,  H01L21/66 ,  H01L21/56 ,  H01L23/532 ,  H01L23/00 ,  H01L23/522 ,  H01L21/78 ,  H01L25/10 ,  H01L21/683 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a through integrated fan-out via (TIV) and a conductive terminal. The RDL structure is disposed on and electrically connected to the die. The TIV is laterally aside the die and extends to contact a bottom surface and a sidewall of a redistribution layer of the RDL structure. The conductive terminal is electrically connected to the die through the RDL structure and the TIV.