公开(公告)号：US11984400B2

公开(公告)日：2024-05-14

申请号：US17303782

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yuan Chang ,  Jui-Lin Chen ,  Kian-Long Lim ,  Feng-Ming Chang

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532 ,  H01L23/535 ,  H01L27/092 ,  H10B10/00

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/53257 ,  H01L23/535 ,  H01L27/0924 ,  H10B10/12

Abstract: An SRAM device and method of forming include pass gate (PG), pull-down (PD), and pull-up (PU) transistors. A first gate line of the PG and a second gate line of the PD and the PU extend in a first direction. A common source/drain of the PG, PD, and PU transistors interposes the first and second gate lines and another source/drain of the PG transistor. A first contact extends from the common source/drain and a second contact extends from the another source/drain. A third contact is disposed above the second contact with a first width in the first direction and a first length in a second direction, first length being greater than the first width.

公开(公告)号：US11264393B2

公开(公告)日：2022-03-01

申请号：US16776205

申请日：2020-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Lin Chen ,  Chao-Yuan Chang ,  Ping-Wei Wang ,  Fu-Kai Yang ,  Ting Fang ,  I-Wen Wu ,  Shih-Hao Lin

IPC: H01L27/11 ,  H01L29/417 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L29/40

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

公开(公告)号：US20210098468A1

公开(公告)日：2021-04-01

申请号：US16776205

申请日：2020-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Lin Chen ,  Chao-Yuan Chang ,  Ping-Wei Wang ,  Fu-Kai Yang ,  Ting Fang ,  I-Wen Wu ,  Shih-Hao Lin

IPC: H01L27/11 ,  H01L29/417 ,  H01L23/522 ,  H01L29/40 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

公开(公告)号：US11682451B2

公开(公告)日：2023-06-20

申请号：US17407005

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yuan Chang ,  Kian-Long Lim ,  Jui-Lin Chen ,  Feng-Ming Chang

IPC: G11C11/419 ,  G11C11/412 ,  H10B10/00

CPC classification number: G11C11/412 ,  G11C11/419 ,  H10B10/12 ,  H10B10/18

Abstract: The current disclosure is directed to a SRAM bit cell having a reduced coupling capacitance. In a vertical direction, a wordline “WL” and a bitline “BL” of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, the WL is vertically spaced apart from the BL with one or more metallization level that none of the WL or the BL is formed from. Connection island structures or jumper structures are provided to connect the upper one of the WL or the BL to the transistors of the SRAM cell.

公开(公告)号：US20220384618A1

公开(公告)日：2022-12-01

申请号：US17877221

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Jui-Lin Chen ,  Hsin-Wen Su ,  Kian-Long Lim ,  Bwo-Ning Chen ,  Chih-Hsuan Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

公开(公告)号：US11367494B2

公开(公告)日：2022-06-21

申请号：US17007806

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Shih-Hao Lin ,  Jui-Lin Chen ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H01L21/76 ,  H01L27/108 ,  G11C17/16 ,  H01L27/112 ,  H01L29/06 ,  H01L21/265

Abstract: The present disclosure provides semiconductor device and methods of forming the same. A semiconductor device according to the present disclosure includes a gate structure, a source/drain feature adjacent the gate structure, a dielectric layer disclosed over the gate structure and the source/drain feature, a gate contact disposed in the dielectric layer and over the gate structure, and a source/drain contact disposed in the dielectric layer and over the source/drain feature. The dielectric layer is doped with a dopant and the dopant includes germanium or tin.

公开(公告)号：US20220068413A1

公开(公告)日：2022-03-03

申请号：US17007806

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Shih-Hao Lin ,  Jui-Lin Chen ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: G11C17/16 ,  H01L21/265 ,  H01L29/06 ,  H01L27/112

Abstract: The present disclosure provides semiconductor device and methods of forming the same. A semiconductor device according to the present disclosure includes a gate structure, a source/drain feature adjacent the gate structure, a dielectric layer disclosed over the gate structure and the source/drain feature, a gate contact disposed in the dielectric layer and over the gate structure, and a source/drain contact disposed in the dielectric layer and over the source/drain feature. The dielectric layer is doped with a dopant and the dopant includes germanium or tin.

公开(公告)号：US11239121B2

公开(公告)日：2022-02-01

申请号：US17012530

申请日：2020-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Chen ,  Jui-Lin Chen ,  Yu-Kuan Lin

IPC: H01L21/8238 ,  H01L27/11 ,  H01L23/522 ,  H01L21/768

Abstract: A method of forming a semiconductor device includes providing a structure that includes a substrate, a first fin and a second fin, a first gate structure engaging the first fin, and a second gate structure engaging the second fin; depositing a dielectric layer over the first and second gate structures; etching the dielectric layer, thereby forming a first gate contact opening exposing the first gate structure and a second gate contact opening exposing the second gate structure, wherein the first gate contact opening has a first length that is larger than a second length of the second gate contact opening; and filling the first and second gate contact openings with conductive material, thereby forming a first gate contact engaging the first gate structure and a second gate contact engaging the second gate structure.

公开(公告)号：US11121078B2

公开(公告)日：2021-09-14

申请号：US16573769

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Lin Chen ,  Chao-Yuan Chang ,  Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H01L23/522 ,  G11C5/06 ,  H01L29/78 ,  H01L27/11 ,  H01L27/092 ,  G06F30/394

Abstract: A semiconductor device includes a gate structure, a source/drain, a first via that is disposed over the gate structure and the source/drain, and a first metal line having a more elevated vertical position than the first via in a cross-sectional view. The first via is electrically coupled to both the gate structure and the source/drain. The first metal line and the first via each extends in a first direction. A first distance separates the metal line from the via in a second direction different from the first direction. The first metal line includes a protruding portion that protrudes outwardly in the second direction.

公开(公告)号：US12190943B2

公开(公告)日：2025-01-07

申请号：US18336816

申请日：2023-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yuan Chang ,  Feng-Ming Chang ,  Jui-Lin Chen ,  Kian-Long Lim

IPC: G11C11/412 ,  G11C11/419 ,  H10B10/00

Abstract: The current disclosure is directed to a SRAM bit cell having a reduced coupling capacitance. In a vertical direction, a wordline “WL” and a bitline “BL” of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, the WL is vertically spaced apart from the BL with one or more metallization level that none of the WL or the BL is formed from. Connection island structures or jumper structures are provided to connect the upper one of the WL or the BL to the transistors of the SRAM cell.