公开(公告)号：US10651170B2

公开(公告)日：2020-05-12

申请号：US15646962

申请日：2017-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lung Tung ,  Min-Chang Liang ,  Fang Chen

IPC: H01L27/08 ,  H01L27/12 ,  H01L29/06 ,  H01L49/02 ,  H01L21/84 ,  H01L21/761 ,  G06F17/50 ,  H01L21/762

Abstract: A semiconductor device includes a substrate, a dielectric layer over the substrate, a first resistor element embedded within the dielectric layer, a second resistor element embedded within the dielectric layer, a first doped well within the substrate, the first doped well being aligned with the first resistor element, and a second doped well within the substrate, the second doped well being aligned with the second resistor element, the second doped well being non-contiguous with the first doped well.

公开(公告)号：US20240321958A1

公开(公告)日：2024-09-26

申请号：US18187233

申请日：2023-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lung Tung ,  Xiaodong Wang ,  Jhon Jhy Liaw

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: In an embodiment, a method includes: placing a first cell in a device layout, the first cell defining a first transistor, the first transistor including a first quantity of first nanostructures; placing a second cell in the device layout directly adjacent to the first cell, the second cell defining a second transistor, the second transistor including a second quantity of second nanostructures, the second quantity being different than the first quantity; generating a lithography mask based on the device layout; and manufacturing a semiconductor device using the lithography mask.