公开(公告)号：US11581256B2

公开(公告)日：2023-02-14

申请号：US16696824

申请日：2019-11-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  G06F30/39

摘要： Interconnect structures that maximize integrated circuit (IC) density and corresponding formation techniques are disclosed. An exemplary IC device includes a gate layer extending along a first direction. An interconnect structure disposed over the gate layer includes odd-numbered interconnect routing layers oriented along a second direction that is substantially perpendicular to the first direction and even-numbered interconnect routing layers oriented along a third direction that is substantially parallel to the first direction. In some implementations, a ratio of a gate pitch of the gate layer to a pitch of a first of the even-numbered interconnect routing layers to a pitch of a third of the even-numbered interconnect routing layers is 3:2:4. In some implementations, a pitch of a first of the odd-numbered interconnect routing layers to a pitch of a third of the odd-numbered interconnect routing layers to a pitch of a seventh of the odd-numbered interconnect routing layers is 1:1:2.

公开(公告)号：US20220383944A1

公开(公告)日：2022-12-01

申请号：US17883910

申请日：2022-08-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fang Chen ,  Kuo-Chiang Ting ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC分类号： G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L27/088 ,  H03K19/20

摘要： An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

公开(公告)号：US20220336439A1

公开(公告)日：2022-10-20

申请号：US17850067

申请日：2022-06-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fang Chen ,  Jhon Jhy Liaw

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L27/092 ,  H01L27/118 ,  H01L21/8238

摘要： An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region.

公开(公告)号：US11127742B2

公开(公告)日：2021-09-21

申请号：US16722841

申请日：2019-12-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC分类号： H01L27/088 ,  H01L23/528 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/49 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L27/02

摘要： A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view.

公开(公告)号：US20200098686A1

公开(公告)日：2020-03-26

申请号：US16696824

申请日：2019-11-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC分类号： H01L23/522 ,  G06F17/50 ,  H01L23/528 ,  H01L21/768

摘要： Interconnect structures that maximize integrated circuit (IC) density and corresponding formation techniques are disclosed. An exemplary IC device includes a gate layer extending along a first direction. An interconnect structure disposed over the gate layer includes odd-numbered interconnect routing layers oriented along a second direction that is substantially perpendicular to the first direction and even-numbered interconnect routing layers oriented along a third direction that is substantially parallel to the first direction. In some implementations, a ratio of a gate pitch of the gate layer to a pitch of a first of the even-numbered interconnect routing layers to a pitch of a third of the even-numbered interconnect routing layers is 3:2:4. In some implementations, a pitch of a first of the odd-numbered interconnect routing layers to a pitch of a third of the odd-numbered interconnect routing layers to a pitch of a seventh of the odd-numbered interconnect routing layers is 1:1:2.

公开(公告)号：US10276554B1

公开(公告)日：2019-04-30

申请号：US16008563

申请日：2018-06-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fang Chen ,  Jhon Jhy Liaw

IPC分类号： H01L27/088 ,  H01L27/02 ,  H01L29/06 ,  H01L27/092

摘要： An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and having a one-pitch dimension P. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region. The first filler cell includes a third dielectric gate on a first filler cell boundary and a fourth dielectric gate on a second filler cell boundary.

公开(公告)号：US20230115015A1

公开(公告)日：2023-04-13

申请号：US18064785

申请日：2022-12-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fang Chen ,  Jhon Jhy Liaw

IPC分类号： H01L29/78 ,  H01L21/321 ,  H01L29/45 ,  H01L29/40 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088 ,  H01L23/528 ,  H01L23/522 ,  H01L21/8238 ,  H01L27/092

摘要： The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.

公开(公告)号：US11605637B2

公开(公告)日：2023-03-14

申请号：US17345309

申请日：2021-06-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang ,  Ren-Fen Tsui ,  Shih-Chi Fu ,  Yen-Huei Chen

IPC分类号： H01L27/11 ,  G11C11/418 ,  H01L23/528 ,  H01L27/02

摘要： A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

公开(公告)号：US11508737B2

公开(公告)日：2022-11-22

申请号：US16910498

申请日：2020-06-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fang Chen ,  Kuo-Chiang Ting ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC分类号： H01L27/11 ,  H01L27/11582 ,  H01L49/02 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088

摘要： An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

公开(公告)号：US10770449B2

公开(公告)日：2020-09-08

申请号：US16397021

申请日：2019-04-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fang Chen ,  Jhon Jhy Liaw

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L27/092 ,  H01L27/118 ,  H01L21/8238

摘要： An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region.