公开(公告)号：US09350324B2

公开(公告)日：2016-05-24

申请号：US13727850

申请日：2012-12-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsung-Hsiung Lee ,  Shi-Hung Wang ,  Kuang-Kai Yen ,  Wei-Li Chen ,  Yung-Hsu Chuang ,  Shih-Hung Lan ,  Fan-ming Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H03K3/00 ,  H03K3/012 ,  H03K3/3562 ,  H03K3/356

CPC分类号： H03K3/012 ,  H03K3/356008 ,  H03K3/356043 ,  H03K3/3562

摘要： The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed.

摘要翻译： 本公开涉及一种减少MCML逻辑器件的动态/静态功耗的装置和方法。 为了在断电模式下保持寄存器内容，公开了一种MCML保持锁存器和触发器。 保留MCML架构中的锁存电路用于在断电模式下保留关键寄存器内容，其中包括时钟树路径上的时钟缓冲器的组合逻辑被关闭以减少动态/静态功耗。 MCML保持触发器包括主锁存器和从锁存器，其中在断电模式期间将电源开关加到主锁存器以为主锁存器供电。 从锁存器包括保持有效的下拉电路，以使从锁存器在断电模式期间将数据保持在适当的电压电平。 还公开了其它装置和方法。

公开(公告)号：US20140184296A1

公开(公告)日：2014-07-03

申请号：US13727850

申请日：2012-12-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Tsung-Hsiung Lee ,  Shi-Hung Wang ,  Kuang-Kai Yen ,  Wei-Li Chen ,  Yung-Hsu Chuang ,  Shih-Hung Lan ,  Fan-Ming Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H03K3/012 ,  H03K3/3562 ,  H03K3/037

CPC分类号： H03K3/012 ,  H03K3/356008 ,  H03K3/356043 ,  H03K3/3562

摘要： The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed.

摘要翻译： 本公开涉及一种减少MCML逻辑器件的动态/静态功耗的装置和方法。 为了在断电模式下保持寄存器内容，公开了一种MCML保持锁存器和触发器。 保留MCML架构中的锁存电路用于在断电模式下保留关键寄存器内容，其中包括时钟树路径上的时钟缓冲器的组合逻辑被关闭以减少动态/静态功耗。 MCML保持触发器包括主锁存器和从锁存器，其中在断电模式期间将电源开关加到主锁存器以为主锁存器供电。 从锁存器包括保持有效的下拉电路，以使从锁存器在断电模式期间将数据保持在适当的电压电平。 还公开了其它装置和方法。