公开(公告)号：US11626510B2

公开(公告)日：2023-04-11

申请号：US17582729

申请日：2022-01-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Chi-Hsiang Chang ,  Tzu-Chung Wang ,  Shu-Yuan Ku

IPC分类号： H01L31/119 ,  H01L29/76 ,  H01L29/94 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

摘要： A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.

公开(公告)号：US20240363735A1

公开(公告)日：2024-10-31

申请号：US18763088

申请日：2024-07-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Chi-Hsiang Chang ,  Tzu-Chung Wang ,  Shu-Yuan Ku

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/6681 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/785

摘要： A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.

公开(公告)号：US20240274695A1

公开(公告)日：2024-08-15

申请号：US18644330

申请日：2024-04-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ya-Yi Tsai ,  Chi-Hsiang Chang ,  Shih-Yao Lin ,  Tzu-Chung Wang ,  Shu-Yuan Ku

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/6681 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/785

摘要： A semiconductor device and method of fabricating a semiconductor device involves formation of a trench above a fin (e.g. a fin of a FinFET device) of the semiconductor device and formation of a multi-layer dielectric structure within the trench. The profile of the multi-layer dielectric structure can be controlled depending on the application to reduce shadowing effects and reduce cut failure risk, among other possible benefits. The multi-layer dielectric structure can include two layers, three layers, or any number of layers and can have a stepped profile, a linear profile, or any other type of profile.

公开(公告)号：US20230061323A1

公开(公告)日：2023-03-02

申请号：US17460198

申请日：2021-08-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ya-Yi Tsai ,  Shih-Yao Lin ,  Chi-Hsiang Chang ,  Wei-Han Chen ,  Shu-Yuan Ku

IPC分类号： H01L27/088 ,  H01L21/8234

摘要： A method of fabricating a semiconductor device is described. A substrate is provided. A plurality of fins is formed extending from the substrate, the fins including a first group of active fins arranged in an active region, and including an inactive fin having at least a portion in an inactive region, the active fins separated by first trench regions between adjacent of the active regions, the inactive fin separated from its closest active fin by a second trench region, the second trench region having a greater width than that of a trench region of the first trench regions. A dummy fin is formed on the isolation dielectric in the second trench region, the dummy fin disposed between the first group of active fins and the inactive fin. A dummy gate is formed over the fins. The gate isolation structure is disposed between the dummy fin and the inactive fin and separates regions of the dummy gate.

公开(公告)号：US20220149181A1

公开(公告)日：2022-05-12

申请号：US17582729

申请日：2022-01-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Chi-Hsiang Chang ,  Tzu-Chung Wang ,  Shu-Yuan Ku

IPC分类号： H01L29/66

摘要： A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.