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公开(公告)号：US09195134B2
公开(公告)日：2015-11-24
申请号：US13956962
申请日：2013-08-01
发明人： Chin-Min Huang , Bo-Han Chen , Lun-Wen Yeh , Shun-Shing Yang , Chia-Cheng Chang , Chern-Shyan Tsay , Chien Wen Lai , Hua-Tai Lin
CPC分类号： G06F17/5081 , G03F1/36 , G03F1/70
摘要： Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.
摘要翻译： 提供了一种集成电路（IC）设计方法。 该方法包括接收IC的设计布局，设计布局具有第一主要特征，以及向设计布局添加负辅助特征，其中，所述负辅助特征具有第一宽度，所述负辅助特征将所述第一主要特征 通过第一宽度成为第二主要特征和第三主要特征，并且第一宽度是光刻工艺中的次分辨率。
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公开(公告)号：US11748549B2
公开(公告)日：2023-09-05
申请号：US17236832
申请日：2021-04-21
发明人： Chin-Min Huang , Bo-Han Chen , Cherng-Shyan Tsay , Chien-Wen Lai , Hua-Tai Lin , Chia-Cheng Chang , Lun-Wen Yeh , Shun-Shing Yang
IPC分类号： G06F30/398 , G03F1/36 , G03F1/70
CPC分类号： G06F30/398 , G03F1/36 , G03F1/70
摘要： Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.
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公开(公告)号：US20210240907A1
公开(公告)日：2021-08-05
申请号：US17236832
申请日：2021-04-21
发明人： Chin-Min Huang , Bo-Han Chen , Cherng-Shyan Tsay , Chien-Wen Lai , Hua-Tai Lin , Chia-Cheng Chang , Lun-Wen Yeh , Shun-Shing Yang
IPC分类号： G06F30/398 , G03F1/36 , G03F1/70
摘要： Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.
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公开(公告)号：US20230260838A1
公开(公告)日：2023-08-17
申请号：US18130288
申请日：2023-04-03
发明人： Yuan-Yen LO , Chia-Cheng Chang , Ming-Jhih Kuo , Chien-Yuan Chen
IPC分类号： H01L21/768 , H01L21/8238 , H01L21/285 , H01L21/32
CPC分类号： H01L21/76895 , H01L21/32 , H01L21/28518 , H01L21/76805 , H01L21/76816 , H01L21/823821 , H01L21/823871
摘要： In a method of manufacturing a semiconductor device, initial connection patterns are prepared, initial cutting patterns for cutting the initial connection patterns are prepared, non-functional connection patterns at least from the initial connection patterns are identified, final cutting patterns are prepared from the initial cutting patterns and the non-functional connection patterns, a photo mask is prepared from the final cutting patterns, a photo resist pattern is formed over a target layer by a lithography operation using the photo mask, the target layer is patterned to form openings in the target layer by using the photo resist pattern, and connection layers are formed by filling the openings with a conductive material.
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公开(公告)号：US10990744B2
公开(公告)日：2021-04-27
申请号：US15868113
申请日：2018-01-11
发明人： Chin-Min Huang , Bo-Han Chen , Cherng-Shyan Tsay , Chien Wen Lai , Hua-Tai Lin , Chia-Cheng Chang , Lun-Wen Yeh , Shun-Shing Yang
IPC分类号： G06F30/398 , G03F1/36 , G03F1/70
摘要： Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.
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公开(公告)号：US20160085906A1
公开(公告)日：2016-03-24
申请号：US14949713
申请日：2015-11-23
发明人： Chin-Min Huang , Bo-Han Chen , Cherng-Shyan Tsay , Chien Wen Lai , Hua-Tai Lin , Chia-Cheng Chang , Lun-Wen Yeh , Shun-Shing Yang
CPC分类号： G06F17/5081 , G03F1/36 , G03F1/70
摘要： Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.
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公开(公告)号：US20180137233A1
公开(公告)日：2018-05-17
申请号：US15868113
申请日：2018-01-11
发明人： Chin-Min Huang , Bo-Han Chen , Cherng-Shyan Tsay , Chien Wen Lai , Hua-Tai Lin , Chia-Cheng Chang , Lun-Wen Yeh , Shun-Shing Yang
CPC分类号： G06F17/5081 , G03F1/36 , G03F1/70
摘要： Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.
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公开(公告)号：US09870443B2
公开(公告)日：2018-01-16
申请号：US14949713
申请日：2015-11-23
发明人： Chin-Min Huang , Bo-Han Chen , Cherng-Shyan Tsay , Chien Wen Lai , Hua-Tai Lin , Chia-Cheng Chang , Lun-Wen Yeh , Shun-Shing Yang
CPC分类号： G06F17/5081 , G03F1/36 , G03F1/70
摘要： Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.
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公开(公告)号：US09213233B2
公开(公告)日：2015-12-15
申请号：US13941164
申请日：2013-07-12
发明人： Chia-Cheng Chang , Wei-Kuan Yu , Yen-Hsu Chu , Tsai-Ming Huang , Chin-Min Huang , Cherng-Shyan Tsay , Chien Wen Lai , Hua-Tai Lin
CPC分类号： G03F1/38 , G03F1/36 , G03F7/20 , G03F7/70283 , G03F7/70441
摘要： Provided is an integrated circuit (IC) photo mask. The IC photo mask includes a main feature of the IC, the main feature having a plurality of sides, and a plurality of assist features, the assist features being spaced from each other and spaced from the main feature, wherein each one of the assist features is adjacent to one of the sides, each one of the assist features has an elongated shape along a direction, whereby extending the shape in the direction would intersect at least another one of the assist features and the assist features are sub-resolution correction features for correcting for optical proximity effect in a photolithography process.
摘要翻译： 提供了一种集成电路（IC）光掩模。 IC照片掩模包括IC的主要特征，主要特征具有多个侧面，以及多个辅助特征，辅助特征彼此间隔开并且与主要特征间隔开，其中每个辅助特征 辅助特征中的每一个相邻于一个侧面，每个辅助特征沿着一个方向具有细长形状，由此沿该方向延伸的形状将与辅助特征和辅助特征中的至少另一个相交，具有子分辨率校正特征，用于 在光刻工艺中校正光学邻近效应。
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公开(公告)号：US20150040081A1
公开(公告)日：2015-02-05
申请号：US13956962
申请日：2013-08-01
发明人： Chin-Min Huang , Bo-Han Chen , Lun-Wen Yeh , Shun-Shing Yang , Chia-Cheng Chang , Chern-Shyan Tsay , Chien Wen Lai , Hua-Tai Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G03F1/70
摘要： Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.
摘要翻译： 提供了一种集成电路（IC）设计方法。 该方法包括接收IC的设计布局，设计布局具有第一主要特征，以及向设计布局添加负辅助特征，其中，所述负辅助特征具有第一宽度，所述负辅助特征将所述第一主要特征 通过第一宽度成为第二主要特征和第三主要特征，并且第一宽度是光刻工艺中的次分辨率。
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