公开(公告)号：US20220367725A1

公开(公告)日：2022-11-17

申请号：US17319783

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao LIN ,  Chong-De LIEN ,  Chih-Chuan YANG ,  Chih-Yu HSU ,  Ming-Shuan LI ,  Hsin-Wen SU

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/24 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238

Abstract: A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.

公开(公告)号：US20230395703A1

公开(公告)日：2023-12-07

申请号：US18447932

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao LIN ,  Chia-Hung CHOU ,  Chih-Hsuan CHEN ,  Ping-En CHENG ,  Hsin-Wen SU ,  Chien-Chih LIN ,  Szu-Chi YANG

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L29/66553 ,  H01L21/823468 ,  H01L29/7851 ,  H01L21/823431 ,  H01L29/6656

Abstract: A semiconductor structure includes substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers extend in an X-direction and over the substrate. The semiconductor layers are spaced apart from each other in a Z-direction. The source/drain features are on opposite sides of the semiconductor layers in the X-direction. The metal oxide layers cover bottom surfaces of the semiconductor layers. The gate structure wraps around the semiconductor layers and the metal oxide layers. The metal oxide layers are in contact with the gate structure.

公开(公告)号：US20220384609A1

公开(公告)日：2022-12-01

申请号：US17332025

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao LIN ,  Chia-Hung CHOU ,  Chih-Hsuan CHEN ,  Ping-En CHENG ,  Hsin-Wen SU ,  Chien-Chih LIN ,  Szu-Chi YANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor structure includes: a semiconductor substrate; a first source/drain feature and a second source/drain feature over the semiconductor substrate; and semiconductor layers extending longitudinally in a first direction and connecting the first source/drain feature and the second source/drain feature. The semiconductor layers are spaced apart from each other in a second direction perpendicular to the first direction. The semiconductor structure further includes inner spacers each between two adjacent semiconductor layers; metal oxide layers interposing between the inner spacers and the semiconductor layers; and a gate structure wrapping around the semiconductor layers and the metal oxide layers.

公开(公告)号：US20220336639A1

公开(公告)日：2022-10-20

申请号：US17465766

申请日：2021-09-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Chih LIN ,  Hsiu-Hao TSAO ,  Szu-Chi YANG ,  Shih-Hao LIN ,  Yu-Jiun PENG ,  Chang-Jhih SYU ,  An Chyi WEI

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/3065

Abstract: A method of fabricating a device includes providing a fin having an epitaxial layer stack with a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes exposing lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers within a source/drain region of the semiconductor device. In some examples, the method further includes etching the exposed lateral surfaces of the plurality of dummy layers to form recesses and forming an inner spacer within each of the recesses, where the inner spacer includes a sidewall profile having a convex shape. In some cases, and after forming the inner spacer, the method further includes performing a sheet trim process to tune the sidewall profile of the inner spacer such that the convex shape of the sidewall profile becomes a substantially vertical sidewall surface after the sheet trim process.

公开(公告)号：US20230268272A1

公开(公告)日：2023-08-24

申请号：US18308875

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-En CHENG ,  Wei-Li HUANG ,  Kun-Ming TSAI ,  Shih-Hao LIN

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76829 ,  H01L21/76841

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect structure over the substrate. The chip structure includes a conductive pad over the interconnect structure. The chip structure includes a passivation layer covering the interconnect structure and exposing the conductive pad. The chip structure includes a first etch stop layer over the passivation layer. The chip structure includes a first buffer layer over the first etch stop layer. The first etch stop layer and the first buffer layer are made of different materials. The chip structure includes a second etch stop layer over the first buffer layer. The second etch stop layer and the first buffer layer are made of different materials. The chip structure includes a device element over the second etch stop layer.

公开(公告)号：US20220367726A1

公开(公告)日：2022-11-17

申请号：US17319794

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao LIN ,  Chih-Chuan YANG ,  Chih-Hsuan CHEN ,  Bwo-Ning CHEN ,  Cha-Hon CHOU ,  Hsin-Wen SU ,  Chih-Hsiang HUANG

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/24 ,  H01L29/423 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8238 ,  H01L29/66

Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

公开(公告)号：US20220328561A1

公开(公告)日：2022-10-13

申请号：US17408145

申请日：2021-08-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jui-Lin CHEN ,  Chenchen Jacob WANG ,  Hsin-Wen SU ,  Ping-Wei WANG ,  Yuan-Hao CHANG ,  Po-Sheng LU ,  Shih-Hao LIN

IPC: H01L27/22

Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.

公开(公告)号：US20220320337A1

公开(公告)日：2022-10-06

申请号：US17410048

申请日：2021-08-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Wei CHEN ,  Chi-Sheng LAI ,  Shih-Hao LIN ,  Jian-Hao CHEN ,  Kuo-Feng YU

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/08

Abstract: A transistor is provided. The transistor includes a first source/drain epitaxial feature, a second source/drain epitaxial feature, and two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The two or more semiconductor layers comprise different materials. The transistor further includes a gate electrode layer surrounding at least a portion of the two or more semiconductor layers, wherein the transistor has two or more threshold voltages.

公开(公告)号：US20240324245A1

公开(公告)日：2024-09-26

申请号：US18731494

申请日：2024-06-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jui-Lin CHEN ,  Hsin-Wen SU ,  Shih-Hao LIN ,  Po-Sheng LU ,  Chenchen Jacob WANG ,  Yuan Hao CHANG ,  Ping-Wei WANG

IPC: H10B61/00 ,  H10N50/80

CPC classification number: H10B61/22 ,  H10N50/80

Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.

公开(公告)号：US20240395860A1

公开(公告)日：2024-11-28

申请号：US18790496

申请日：2024-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chien-Chih LIN ,  Yun-Ju PAN ,  Szu-Chi YANG ,  Jhih-Yang YAN ,  Shih-Hao LIN ,  Chung-Shu WU ,  Te-An YU ,  Shih-Chiang CHEN

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.