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公开(公告)号：US12094872B2
公开(公告)日：2024-09-17
申请号：US17643651
申请日：2021-12-10
发明人： Chung-Hui Chen , Wan-Te Chen , Shu-Wei Chung , Tung-Heng Hsieh , Tzu-Ching Chang , Tsung-Hsin Yu , Yung Feng Chang
IPC分类号： H01L27/06 , H01L29/06 , H01L29/423 , H01L29/786
CPC分类号： H01L27/0629 , H01L29/0653 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： A semiconductor device includes a substrate. A first nanosheet structure and a second nanosheet structure are disposed on the substrate. Each of the first and second nanosheet structures have at least one nanosheet forming source/drain regions and a gate structure including a conductive gate contact. A first oxide structure is disposed on the substrate between the first and second nanosheet structures. A conductive terminal is disposed in or on the first oxide structure. The conductive terminal, the first oxide structure and the gate structure of the first nanosheet structure define a capacitor.
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公开(公告)号：US10861807B2
公开(公告)日：2020-12-08
申请号：US16297938
申请日：2019-03-11
发明人： Shu-Wei Chung , Yen-Sen Wang
IPC分类号： H01L23/00 , H01L21/768 , G06F30/394
摘要： A method includes forming a seed layer on a semiconductor wafer, coating a photo resist on the seed layer, performing a photo lithography process to expose the photo resist, and developing the photo resist to form an opening in the photo resist. The seed layer is exposed, and the opening includes a first opening of a metal pad and a second opening of a metal line connected to the first opening. At a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first opening are greater than 90 degrees. The method further includes plating the metal pad, the metal line, and the metal patch in the opening in the photo resist, removing the photo resist, and etching the seed layer to leave the metal pad, the metal line and the metal patch.
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公开(公告)号：US20240234301A1
公开(公告)日：2024-07-11
申请号：US18616195
申请日：2024-03-26
发明人： Shu-Wei Chung , Yen-Sen Wang
IPC分类号： H01L23/522 , H01L21/768 , H01L23/528
CPC分类号： H01L23/5226 , H01L21/76807 , H01L21/76877 , H01L23/528
摘要： A semiconductor structure and method of forming the same are provided. The semiconductor structure has a conductive structure. The semiconductor structure includes a first conductive line, a second conductive line, a third conductive line and a conductive via. The first conductive line and the second conductive line are located in a first dielectric layer and extend along a first direction. The first conductive line and the second conductive line are spaced from each other by the first dielectric layer therebetween. The third conductive line is located in a second dielectric layer and extends along a second direction. The conductive via is vertically between the first conductive line and the third conductive line, and between the second conductive line and the third conductive line. The conductive via, in a vertical direction, is overlapped with a portion of the first dielectric layer that is laterally between the first conductive line and the second conductive line.
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公开(公告)号：US20220405457A1
公开(公告)日：2022-12-22
申请号：US17476615
申请日：2021-09-16
发明人： Shu-Wei Chung , Tung-Heng Hsieh , Chung-Hui Chen , Chung-Yi Lin
IPC分类号： G06F30/392 , G06F30/398 , G06F30/323
摘要： An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.
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公开(公告)号：US20200161260A1
公开(公告)日：2020-05-21
申请号：US16297938
申请日：2019-03-11
发明人： Shu-Wei Chung , Yen-Sen Wang
IPC分类号： H01L23/00 , G06F17/50 , H01L21/768
摘要： A method includes forming a seed layer on a semiconductor wafer, coating a photo resist on the seed layer, performing a photo lithography process to expose the photo resist, and developing the photo resist to form an opening in the photo resist. The seed layer is exposed, and the opening includes a first opening of a metal pad and a second opening of a metal line connected to the first opening. At a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first are greater than 90 degrees. The method further includes plating the metal pad, the metal line, and the metal patch in the opening in the photo resist, removing the photo resist, and etching the seed layer to leave the metal pad, the metal line and the metal patch.
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公开(公告)号：US20240362392A1
公开(公告)日：2024-10-31
申请号：US18769843
申请日：2024-07-11
发明人： Shu-Wei Chung , Tung-Heng Hsieh , Chung-Hui Chen , Chung-Yi Lin
IPC分类号： G06F30/392 , G06F30/323 , G06F30/398 , G06F111/20
CPC分类号： G06F30/392 , G06F30/323 , G06F30/398 , G06F2111/20
摘要： An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.
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公开(公告)号：US12073165B2
公开(公告)日：2024-08-27
申请号：US17476615
申请日：2021-09-16
发明人： Shu-Wei Chung , Tung-Heng Hsieh , Chung-Hui Chen , Chung-Yi Lin
IPC分类号： G06F30/30 , G06F30/323 , G06F30/392 , G06F30/398 , G06F111/20
CPC分类号： G06F30/392 , G06F30/323 , G06F30/398 , G06F2111/20
摘要： An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.
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公开(公告)号：US09570584B2
公开(公告)日：2017-02-14
申请号：US14459829
申请日：2014-08-14
发明人： Chih Hsiung Lin , Chia-Der Chang , Pin-Cheng Hsu , Min-Hsiung Chiang , Shu-Wei Chung , Hao Wen Hsu
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78 , H01L29/08 , H01L29/165
CPC分类号： H01L29/66636 , H01L29/0847 , H01L29/165 , H01L29/66659 , H01L29/7835 , H01L29/7847 , H01L29/7848
摘要： Some embodiments of the present disclosure provide a semiconductor device including a substrate and a gate structure on the substrate. A first well region of a first conductivity type is in the substrate, close to a first sidewall of the gate structure. A second well region of a second conductivity type is also in the substrate close to the second sidewall of the gate structure. A conductive region is disposed in the second well region. The conductive region can be an epitaxy region. A chemical composition inside the second well region between the conductive region and the gate structure is essentially homogeneous as a chemical composition throughout the second well region.
摘要翻译： 本公开的一些实施例提供了一种在衬底上包括衬底和栅极结构的半导体器件。 第一导电类型的第一阱区位于衬底中，靠近栅极结构的第一侧壁。 第二导电类型的第二阱区也在靠近栅极结构的第二侧壁的衬底中。 导电区域设置在第二阱区域中。 导电区域可以是外延区域。 导电区域和栅极结构之间的第二阱区域内的化学组成在整个第二阱区域中作为化学组成基本均匀。
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