公开(公告)号：US20220406716A1

公开(公告)日：2022-12-22

申请号：US17351711

申请日：2021-06-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wan-Yu LO ,  Chung-Hsing WANG ,  Chin-Shen LIN ,  Kuo-Nan YANG ,  Meng-Xiang LEE ,  Hao-Tien KAN ,  Jhih-Hong YE

IPC分类号： H01L23/528 ,  H01L23/522

摘要： Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.

公开(公告)号：US20150095869A1

公开(公告)日：2015-04-02

申请号：US14039423

申请日：2013-09-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Min FU ,  Wan-Yu LO ,  Chin-Chou LIU ,  Huan Chi TSENG

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  G06F2217/14 ,  Y02P90/265

摘要： A method of making a semiconductor device includes arranging a first cell and a second cell, determining, by a processor, a first pattern density of a first cell, determining a second pattern density of a second cell, determining a pattern density gradient from the first pattern density to the second pattern density, determining whether the pattern density gradient exceeds a pattern density gradient threshold, and indicating a design change if the pattern density gradient exceeds than the pattern density gradient threshold.

摘要翻译： 制造半导体器件的方法包括布置第一单元和第二单元，由处理器确定第一单元的第一图案密度，确定第二单元的第二图案密度，从第一单元确定图案密度梯度 图案密度到第二图案密度，确定图案密度梯度是否超过图案密度梯度阈值，并且如果图案密度梯度超过图案密度梯度阈值则指示设计改变。

公开(公告)号：US20220358271A1

公开(公告)日：2022-11-10

申请号：US17814016

申请日：2022-07-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chin-Shen LIN ,  Ming-Hsien LIN ,  Wan-Yu LO ,  Meng-Xiang LEE

IPC分类号： G06F30/3308 ,  G06F30/392

摘要： Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. A layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. Two first vias are formed over and in contact with the metal segment in the layout. EM rule is kept on the metal segment when a distance between the two first vias is greater than a threshold distance. The EM rule is relaxed on the metal segment when the distance between the two first vias is less than or equal to the threshold distance.

公开(公告)号：US20150161318A1

公开(公告)日：2015-06-11

申请号：US14625147

申请日：2015-02-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chung-Min FU ,  Wan-Yu LO ,  Chin-Chou LIU ,  Huan Chi TSENG

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  G06F2217/14 ,  Y02P90/265

摘要： A method of making a semiconductor device includes determining, by a processor, a first pattern density of a first region, determining a second pattern density of a second region, determining a pattern density gradient from the first region to the second region, determining whether the pattern density gradient exceeds a pattern density gradient threshold and performing a placement or a routing of the semiconductor device if the pattern density gradient is less than or equal to the pattern density gradient threshold.

摘要翻译： 制造半导体器件的方法包括由处理器确定第一区域的第一图案密度，确定第二区域的第二图案密度，确定从第一区域到第二区域的图案密度梯度，确定是否 图案密度梯度超过图案密度梯度阈值，并且如果图案密度梯度小于或等于图案密度梯度阈值，则执行半导体器件的放置或布线。

公开(公告)号：US20210248297A1

公开(公告)日：2021-08-12

申请号：US17245130

申请日：2021-04-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wan-Yu LO ,  Kuo-Nan YANG ,  Chin-Shen LIN ,  Chung-Hsing WANG

IPC分类号： G06F30/392 ,  G06F30/398

摘要： In a method, cell placement is performed to place a plurality of cells into a region of an integrated circuit (IC). A thermal analysis is performed to determine whether the region of the IC is thermally stable at an operating condition. In response to a determination that the region of the IC is thermally unstable, at least one of a structure or the operating condition of the region of the IC is changed. After the thermal analysis, routing is performed to route a plurality of nets interconnecting the placed cells. At least one of the cell placement, the thermal analysis, the changing or the routing is executed by a processor.

公开(公告)号：US20210209278A1

公开(公告)日：2021-07-08

申请号：US17209393

申请日：2021-03-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chin-Shen LIN ,  Ming-Hsien LIN ,  Wan-Yu LO ,  Meng-Xiang LEE

IPC分类号： G06F30/3308 ,  G06F30/392

摘要： Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. EM rule is kept on the metal segment when a single via is formed over and in contact with the metal segment in the layout. The EM rule is relaxed on the metal segment when two first vias are formed over and in contact with the metal segment in the layout. The two first vias have the same current direction.