公开(公告)号：US11257963B1

公开(公告)日：2022-02-22

申请号：US17100562

申请日：2020-11-20

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yu-Chu Lin ,  Chi-Chung Jen ,  Wen-Chih Chiang ,  Ming-Hong Su ,  Yung-Han Chen ,  Mei-Chen Su ,  Chia-Ming Pan

IPC分类号： H01L29/78 ,  G11C16/14 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11524 ,  H01L27/11519

摘要： In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.

公开(公告)号：US20210327951A1

公开(公告)日：2021-10-21

申请号：US16851277

申请日：2020-04-17

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Keng-Ying Liao ,  Huai-Jen Tung ,  Chih Wei Sung ,  Po-Zen Chen ,  Yu-Chien Ku ,  Yu-Chu Lin ,  Chi-Chung Jen ,  Yen-Jou Wu ,  Tsun-Kai Tsao ,  Y.L. Yang

IPC分类号： H01L27/146

摘要： A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.

公开(公告)号：US11903193B2

公开(公告)日：2024-02-13

申请号：US17863749

申请日：2022-07-13

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chi-Chung Jen ,  Yu-Chu Lin ,  Y. C. Kuo ,  Wen-Chih Chiang ,  Keng-Ying Liao ,  Huai-Jen Tung

IPC分类号： H01L21/28 ,  H10B41/46 ,  H01L29/423 ,  H10B41/30 ,  H01L29/51

CPC分类号： H10B41/46 ,  H01L29/40114 ,  H01L29/42336 ,  H10B41/30 ,  H01L29/513

摘要： A MOSFET device and method of making, the device including a floating gate layer formed within a trench in a substrate, a tunnel dielectric layer located on sidewalls and a bottom of the trench, a control gate dielectric layer located on a top surface of the floating gate layer, a control gate layer located on a top surface of the control gate dielectric layer and sidewall spacers located on sidewalls of the control gate dielectric layer and the control gate layer.

公开(公告)号：US20220028993A1

公开(公告)日：2022-01-27

申请号：US17496839

申请日：2021-10-08

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yu-Chu Lin ,  Chia-Ming Pan ,  Chi-Chung Jen ,  Wen-Chih Chiang ,  Keng-Ying Liao ,  Huai-jen Tung

IPC分类号： H01L29/423 ,  H01L27/11521 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

摘要： A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.

公开(公告)号：US11888074B2

公开(公告)日：2024-01-30

申请号：US17868192

申请日：2022-07-19

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yu-Chu Lin ,  Chi-Chung Jen ,  Yi-Ling Liu ,  Wen-Chih Chiang ,  Keng-Ying Liao ,  Huai-Jen Tung

IPC分类号： H01L29/788 ,  H01L21/265 ,  H01L21/28 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H10B41/30

CPC分类号： H01L29/7883 ,  H01L21/26513 ,  H01L29/40114 ,  H01L29/41725 ,  H01L29/42324 ,  H01L29/66492 ,  H01L29/66825 ,  H01L29/7833 ,  H10B41/30

摘要： A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

公开(公告)号：US11792981B2

公开(公告)日：2023-10-17

申请号：US17000613

申请日：2020-08-24

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chi-Chung Jen ,  Yu-Chu Lin ,  Y. C. Kuo ,  Wen-Chih Chiang ,  Keng-Ying Liao ,  Huai-Jen Tung

IPC分类号： H01L29/423 ,  H10B41/46 ,  H01L21/28 ,  H10B41/30 ,  H01L29/51

CPC分类号： H10B41/46 ,  H01L29/40114 ,  H01L29/42336 ,  H10B41/30 ,  H01L29/513

摘要： A MOSFET device and method of making, the device including a floating gate layer formed within a trench in a substrate, a tunnel dielectric layer located on sidewalls and a bottom of the trench, a control gate dielectric layer located on a top surface of the floating gate layer, a control gate layer located on a top surface of the control gate dielectric layer and sidewall spacers located on sidewalls of the control gate dielectric layer and the control gate layer.

公开(公告)号：US11183572B2

公开(公告)日：2021-11-23

申请号：US16852654

申请日：2020-04-20

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yu-Chu Lin ,  Chia-Ming Pan ,  Chi-Chung Jen ,  Wen-Chih Chiang ,  Keng-Ying Liao ,  Huai-jen Tung

IPC分类号： H01L29/423 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/66 ,  H01L21/28

摘要： A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.

公开(公告)号：US20240136444A1

公开(公告)日：2024-04-25

申请号：US18394895

申请日：2023-12-22

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yu-Chu Lin ,  Chi-Chung Jen ,  Wen-Chih Chiang ,  Yi-Ling Liu ,  Huai-Jen Tung ,  Keng-Ying Liao

IPC分类号： H01L29/788 ,  H01L21/265 ,  H01L21/28 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H10B41/30

CPC分类号： H01L29/7883 ,  H01L21/26513 ,  H01L29/40114 ,  H01L29/41725 ,  H01L29/42324 ,  H01L29/66492 ,  H01L29/66825 ,  H01L29/7833 ,  H10B41/30

摘要： A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

公开(公告)号：US20230343844A1

公开(公告)日：2023-10-26

申请号：US18337383

申请日：2023-06-19

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yu-Chu Lin ,  Chia-Ming Pan ,  Chi-Chung Jen ,  Wen-Chih Chiang ,  Huai-Jen Tung ,  Keng-Ying Liao

IPC分类号： H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

CPC分类号： H01L29/42328 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

摘要： A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.

公开(公告)号：US11728399B2

公开(公告)日：2023-08-15

申请号：US17496839

申请日：2021-10-08

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yu-Chu Lin ,  Chia-Ming Pan ,  Chi-Chung Jen ,  Wen-Chih Chiang ,  Keng-Ying Liao ,  Huai-jen Tung

IPC分类号： H01L21/28 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H10B41/30

CPC分类号： H01L29/42328 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

摘要： A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.