公开(公告)号：US20230261004A1

公开(公告)日：2023-08-17

申请号：US17674348

申请日：2022-02-17

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Harry-Hak-Lay CHUANG ,  Kuo-Ching HUANG ,  Wei-Cheng WU ,  Hsin Fu LIN ,  Henry WANG ,  Chien Hung LIU ,  Tsung-Hao YEH ,  Hsien Jung CHEN

IPC分类号： H01L27/12 ,  H01L21/762 ,  H01L29/66

CPC分类号： H01L27/1203 ,  H01L21/76251 ,  H01L29/66772

摘要： A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device on the top semiconductor layer.

公开(公告)号：US20230187499A1

公开(公告)日：2023-06-15

申请号：US18106001

申请日：2023-02-06

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yun-Chi WU ,  Tsung-Yu YANG ,  Cheng-Bo SHU ,  Chien Hung LIU

IPC分类号： H01L29/08 ,  H01L29/40 ,  H01L21/3213 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L29/66 ,  H01L21/027 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02

CPC分类号： H01L29/0847 ,  H01L21/266 ,  H01L21/0276 ,  H01L21/02164 ,  H01L21/2652 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/401 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/66545 ,  H10B10/12

摘要： A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

公开(公告)号：US20240258374A1

公开(公告)日：2024-08-01

申请号：US18432471

申请日：2024-02-05

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yun-Chi WU ,  Tsung-Yu YANG ,  Cheng-Bo SHU ,  Chien Hung LIU

IPC分类号： H01L29/08 ,  H01L21/02 ,  H01L21/027 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC分类号： H01L29/0847 ,  H01L21/02164 ,  H01L21/0276 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H10B10/12

摘要： A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.