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公开(公告)号：US20230387105A1
公开(公告)日：2023-11-30
申请号：US18447367
申请日：2023-08-10
发明人： Yu-Tso Lin , Chih-Hsien Chang , Min-Shueh Yuan , Robert Bogdan Staszewski , Seyednaser Pourmousavian
CPC分类号： H01L27/0629 , G11C16/30 , H02M3/07 , H01L27/0788 , H01L29/94
摘要： A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.
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2.发明申请公开(公告)号：US20200244271A1
公开(公告)日：2020-07-30
申请号：US16851452
申请日：2020-04-17
摘要： Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.
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3.发明申请公开(公告)号：US20190068201A1
公开(公告)日：2019-02-28
申请号：US16106163
申请日：2018-08-21
摘要： Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.
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4.发明授权公开(公告)号：US11349484B2
公开(公告)日：2022-05-31
申请号：US17177442
申请日：2021-02-17
摘要： Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.
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公开(公告)号：US10277117B2
公开(公告)日：2019-04-30
申请号：US15602252
申请日：2017-05-23
发明人： Yu-Tso Lin , Chih-Hsien Chang , Min-Shueh Yuan , Robert Bogdan Staszewski , Seyednaser Pourmousavian
IPC分类号： H03L5/00 , H02M3/07 , H01L29/94 , H03K19/0185
摘要： A device includes a level shifter and a voltage multiplier. The level shifter is responsive to a first clock signal configured to shift the first clock signal to a second clock signal at a higher level than the first clock signal based on a node voltage. The voltage multiplier is responsive to the second clock signal for generating the node voltage. The node voltage is output from the voltage multiplier for driving a load and is further fed back to the level shifter for generating the second clock signal.
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公开(公告)号：US20180342495A1
公开(公告)日：2018-11-29
申请号：US15602246
申请日：2017-05-23
发明人： Yu-Tso Lin , Chih-Hsien Chang , Min-Shueh Yuan , Robert Bogdan Staszewski , Seyednaser Pourmousavian
摘要： A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.
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公开(公告)号：US20140282331A1
公开(公告)日：2014-09-18
申请号：US13852080
申请日：2013-03-28
发明人： Min-Shueh Yuan , Chao-Chieh Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Among other things, one or more techniques and systems for generating a common design rule check (DRC) rule set for verification of a design layout and for generating a common dummy insertion utility for design layout processing are provided. That is, the common DRC rule set comprises a set of design rules having design rule constraint values corresponding to a restriction threshold, such as a most restrictive value. The common dummy insertion utility is used to insert dummy polygons into a design layout according to a dummy size constraint and a dummy spacing constraint. The design layout is verified as compliant with the common DRC rule set. Once verified, the design layout can be converted from a universal design layout format to a target metal scheme to create a transformed design layout. In this way, design layouts, formatted according to the universal design layout, can be transformed to other formats.
摘要翻译： 提供了一种或多种用于生成用于验证设计布局并用于生成用于设计布局处理的公共虚拟插入实用程序的公共设计规则检查（DRC）规则集的技术和系统。 也就是说，普通DRC规则集包括一组设计规则，其具有对应于限制阈值（例如最严格的值）的设计规则约束值。 通常的虚拟插入实用程序用于根据虚拟大小约束和虚拟间隔约束将虚拟多边形插入到设计布局中。 验证设计布局符合常规DRC规则集。 一旦验证，设计布局可以从通用设计布局格式转换为目标金属方案，以创建转换后的设计布局。 以这种方式，根据通用设计布局格式化的设计布局可以转换为其他格式。
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公开(公告)号：US11764211B2
公开(公告)日：2023-09-19
申请号：US16936499
申请日：2020-07-23
发明人： Yu-Tso Lin , Chih-Hsien Chang , Min-Shueh Yuan , Robert Bogdan Staszewski , Seyednaser Pourmousavian
CPC分类号： H01L27/0629 , G11C16/30 , H01L27/0788 , H01L29/94 , H02M3/07
摘要： A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.
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9.发明申请公开(公告)号：US20210184681A1
公开(公告)日：2021-06-17
申请号：US17177442
申请日：2021-02-17
摘要： Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.
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公开(公告)号：US10756083B2
公开(公告)日：2020-08-25
申请号：US15602246
申请日：2017-05-23
发明人： Yu-Tso Lin , Chih-Hsien Chang , Min-Shueh Yuan , Robert Bogdan Staszewski , Seyednaser Pourmousavian
摘要： A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.
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